UM0434 datasheet(45/390 Pages) STMICROELECTRONICS

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UM0434

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The PVR contains fields to specify a particular implementation of an e200z3 family member.

Interface signals

p_pvrin[16:31] provide the contents of bits 48–63.

4.4.4

System version register (SVR)

The system version register (SVR) contains system version information for an e200z3-

based SoC.

SVR specifies a particular implementation of an e200z3-based system.

4.5

Registers for integer operations

This section describes the registers for integer operations.

4.5.1

General purpose registers (GPRs)

Book E implementations provide 32 GPRs (GPR0–GPR31) for integer operations. The

instruction formats provide 5-bit fields for specifying the GPRs for use in executing the

instruction. Each GPR is a 64-bit register and can contain address and integer data,

although all instructions except SPE APU vector instructions use and return 32-bit values in

GPR bits 32–63.

Table 11.

PVR field descriptions

Bits

Name

Description

32–35 Manufacturer ID Manufacturer ID. Freescale is 0b1000.

36–37

—

Reserved, should be cleared.

38–43

Type

Identifies the processor type. For the e200z3, this field has a value of 0b01_0001.

44–47

Version

Identifies the version of the processor and any optional elements. For e200z3, this field

has a value of 0010.

48–55

MBG Use

Distinguishes different system variants; provided by the

p_pvrin[16:23] inputs.

56–59

Major Rev

Distinguishes different implementations of the version; provided by the

p_pvrin[24:27]

inputs.

60–63

MBG ID

Provided by the

p_pvrin[28:31] input signals.

Figure 4.

System version register (SVR)

Field

Version

Reset

SoC-dependent value (determined by

p_sysvers[0:31] on the e200z3 core)

R/W

Read only

SPR

SPR 1023

Table 12.

SVR field description

Bits

Name

Description

32–63

Version Distinguishes different system variants, and is provided by the

p_sysvers[0:31] inputs.

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