UM0434 datasheet(32/390 Pages) STMICROELECTRONICS

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UM0434

e200z3 core complex overview

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The integer execution unit consists of a 32-bit arithmetic unit, a logic unit, a 32-bit barrel

shifter, a mask-insertion unit, a condition register manipulation unit, a count-leading-zeros

unit, a 32

× 32 hardware multiplier array, result feed-forward hardware, and support

hardware for division.

Most arithmetic and logical operations are executed in a single cycle with the exception of

the divide instructions. A count-leading-zeros unit operates in a single clock cycle.

The instruction unit contains a program counter incrementer and a dedicated branch

address adder to minimize delays during change-of-flow operations. Sequential prefetching

is performed to ensure a supply of instructions into the execution pipeline. Branch target

prefetching is performed to accelerate taken branches. Prefetched instructions are placed

into an instruction buffer capable of holding six instructions.

Conditional branches that are not taken and not folded execute in a single cycle. Branches

with successful target prefetching that are not folded have an effective execution time of

1 cycle. All other taken branches have an execution time of 2 clocks.

Memory load and store operations are provided for byte, half-word, word (32-bit), and

double-word data with automatic zero or sign extension of byte and half-word load data as

well as optional byte reversal of data. These instructions can be pipelined to allow effective

single-cycle throughput. Load and store multiple word instructions allow low-overhead

context save and restore operations. The load/store unit (LSU) contains a dedicated

effective address adder to optimize effective address generation.

The condition register unit supports the condition register (CR) and condition register

operations defined by the PowerPC architecture. The CR consists of eight 4-bit fields that

reflect the results of certain operations generated by instructions such as move, integer and

floating-point compare, arithmetic, and logical instructions. The CR also provides a

mechanism for testing and branching.

Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support

is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with

no software overhead.

The SPE APU supports vector instructions operating on 16- and 32-bit integer and fractional

data types. The vector and scalar floating-point APUs operate on 32-bit IEEE-754 single-

precision floating-point formats, and support single-precision floating-point operations in a

pipelined fashion.

The 64-bit GPRs are used for source and destination operands for all vector instructions,

and there is a unified storage model for single-precision floating-point data types of 32 bits

and the normal integer type. Low-latency integer and floating-point add, subtract, multiply,

divide, compare, and conversion operations are provided, and most operations can be

pipelined.

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