UM0434 datasheet(33/390 Pages) STMICROELECTRONICS

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e200z3 core complex overview

UM0434

34/391

3.6.1

Instruction unit features

The e200z3 instruction unit implements the following:

●

64-bit fetch path that supports fetching of two 32-bit or up to four 16-bit VLE APU

instructions per clock

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Instruction buffer that holds up to seven sequential instructions

●

Dedicated PC (program counter) incrementer supporting instruction fetches

●

Branch processing unit with dedicated branch address adder and branch target buffer

(BTB) supporting single-cycle execution of successfully predicted branches

●

Target instruction buffer that holds up to two prefetched branch target instructions

3.6.2

Integer unit features

The integer unit supports single-cycle execution of most integer instructions:

●

32-bit AU for arithmetic and comparison operations

●

32-bit LU for logical operations

●

32-bit priority encoder for count-leading-zeros function

●

32-bit single-cycle barrel shifter for static shifts and rotates

●

32-bit mask unit for data masking and insertion

●

Divider logic for signed and unsigned divide in 6–16 clocks with minimized execution

timing

●

× 32 hardware multiplier array that supports single cycle 32 × 32 > 32 multiply

3.6.3

Load/Store unit (LSU) features

The e200z3 LSU supports load, store, and load multiple/store multiple instructions:

●

32-bit effective address adder for data memory address calculations

●

Pipelined operation supports throughput of one load or store operation per cycle

●

Dedicated 64-bit interface to memory supports saving and restoring of up to two

registers per cycle for load multiple and store multiple word instructions

3.6.4

Memory management unit (MMU) features

The MMU is a Book E-compliant PowerPC implementation, with the following feature set:

●

32-bit effective-to-real address translation

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8-bit process identifier (PID)

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16-entry, fully associative TLB

●

Support for multiple page sizes (4, 16, 64, 256 Kbytes; 1, 4, 16, 64, 256 Mbytes)

●

Hardware assist for TLB miss exceptions

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Software managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions

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Entry flush protection

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Byte ordering (endianness) configurable on a per-page basis

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