UM0434 datasheet(52/390 Pages) STMICROELECTRONICS

52 / 390 page

UM0434

53/391

Table 22.

SPEFSCR field descriptions

Bits

Name

Description

SOVH

Summary integer overflow high. Set whenever an instruction sets OVH and remains set until it is

cleared by an mtspr specifying the SPEFSCR.

OVH

Integer overflow high. Set whenever an integer or fractional SPE instruction signals an overflow in

the upper half of the result.

FGH

Embedded floating-point guard bit high. For use by the floating-point round exception handler. It

is cleared by a floating-point data exception for the high elements. FGH corresponds to the high

element result. FGH is cleared by a scalar floating-point instruction.

FXH

Embedded floating-point sticky bit high. Supplied for use by the floating-point round exception

handler. Zeroed if a floating-point data exception occurred for the high elements. FXH

corresponds to the high element result. FXH is cleared by a scalar floating point instruction.

FINVH

Embedded floating-point invalid operation/input error high.

In mode 0, set if the A or B high element operand of a floating-point instruction is Infinity, NaN, or

Denorm, or if the operation is a divide and the high element dividend and divisor are both 0.

In mode 1, FINVH is set on an IEEE754 invalid operation (IEEE754-1985 sec7.1) in the high

element. Cleared by a scalar floating-point instruction.

FDBZH

Embedded floating-point divide by zero high. Set when a floating-point divide instruction executes

with a high element divisor of 0 and the high element dividend is a finite non-zero number.

Cleared by a scalar floating-point instruction.

FUNFH

Embedded floating-point underflow high. Set when the execution of a floating-point instruction

results in an underflow in the high element. FUNFH is cleared by a scalar floating-point

instruction.

FOVFH

Embedded floating-point overflow high. Set when the execution of a floating-point instruction

results in an overflow in the high element. Cleared by a scalar floating point instruction.

40–41

—

Reserved, should be cleared.

FINXS

Embedded floating-point inexact sticky flag. Set under one of the following conditions:

The execution of a floating-point instruction delivers an inexact result for either the low or high

element and no floating-point data exception is taken for either element

A floating-point instruction causes overflow (FOVF=1 or FOVFH=1), but floating-point overflow

exceptions are disabled (FOVFE=0)

A floating-point instruction results in underflow (FUNF=1 or FUNFH=1), but floating-point

underflow exceptions are disabled (FUNFE=0) and no floating-point data exception occurs.

FINXS remains set until it is cleared by an mtspr specifying SPEFSCR.

FINVS

Embedded floating-point invalid operation sticky flag. Set when a floating-point instruction sets

FINVH or FINV. FINVS remains set until it is cleared by an mtspr instruction specifying

SPEFSCR.

FDBZS

Embedded floating-point divide by zero sticky flag. Set when a floating-point divide instruction

sets FDBZH or FDBZ. FDBZS remains set until it is cleared by an mtspr specifying SPEFSCR.

FUNFS

Embedded floating-point underflow sticky flag. Set when a floating-point instruction sets FUNFH

or FUNF. FUNFS remains set until it is cleared by an mtspr specifying SPEFSCR.

FOVFS

Embedded floating-point overflow sticky flag. Set when a floating-point instruction sets FOVFH or

FOVF. FOVFS remains set until it is cleared by an mtspr specifying SPEFSCR.

UM0434 датащи(PDF) 52 Page - STMicroelectronics

UM0434 датащи(HTML) 52 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL