UM0434 datasheet(35/390 Pages) STMICROELECTRONICS

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e200z3 core complex overview

UM0434

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operations, rather than the FPRs defined by the UISA. Most porting of floating-point

operations can be handled by recompiling.

●

String instructions are not implemented on the e200z3 core; therefore, trap emulation

must be provided to ensure backward compatibility.

Supervisor instruction set

The supervisor-mode instruction set defined by the AIM version of the PowerPC architecture

is compatible with the e200z3 core with the following exceptions:

●

The MMU architecture is different, so some TLB manipulation instructions have

different semantics.

●

Instructions that support BATs and segment registers are not implemented.

3.7.2

Memory subsystem

Both Book E and the AIM version of the PowerPC architecture provide separate instruction

and data memory resources. The e200z3 core provides additional cache control features,

including cache locking.

3.7.3

Interrupt handling

Exception handling is generally the same as that defined in the AIM version of the PowerPC

architecture for the e200z3 core, with the following differences:

●

Book E defines a new critical interrupt, providing an interrupt nesting. The critical

interrupt includes critical input and watchdog timer time-out inputs.

●

The debug interrupt differs from the Book E and from the AIM definition. It defines the

Return from Debug Interrupt instruction, rfdi, and two debug save/restore registers,

DSRR0 and DSRR1.

●

Book E processors can use IVPR and the IVORs to set exception vectors individually,

but they can be set to the address offsets defined in the OEA to provide compatibility.

●

Unlike the AIM version of the PowerPC architecture, Book E does not define a reset

vector; execution begins at a fixed virtual address, 0xFFFF_FFFC. The e200z3 allows

this to be hard-wired to any page.

●

Some Book E and e200z3 core-specific SPRs are different from those defined in the

AIM version of the PowerPC architecture, particularly those related to MMU functions.

Much of this information has been moved to the new exception syndrome register

(ESR).

●

Timer services are generally compatible. However, Book E defines a decrementer

auto-reload feature, and two critical-type interrupts—the fixed-interval timer and the

watchdog timer interrupts—all of which are implemented in the e200z3 core.

See

Chapter 3.5 for overview of Interrupts and exception handling capabilities.

3.7.4

Memory management

The e200z3 core implements a straightforward virtual address space that complies with the

Book E MMU definition, which eliminates segment registers and block address translation

resources. Book E defines resources for multiple, variable page sizes that can be configured

in a single implementation. TLB management is provided with new instructions and SPRs.

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