UM0434 datasheet(43/390 Pages) STMICROELECTRONICS

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UM0434

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SPE

SPE available.

0 Execution of SPE APU vector instructions is disabled. Instead, the SPE

unavailable exception is taken, and ESR[SPE] is set.

1 Execution of SPE APU vector instructions is enabled.

39–44

—

Reserved, should be cleared.

Wait state (power management) enable. Defined as optional by Book E and

implemented in the e200z3.

0 Power management is disabled.

1 Power management is enabled. The processor can enter a power-saving mode

when additional conditions are present. The mode chosen is determined by

HID0[DOZE,NAP,SLEEP], described in

Section 4.13.1: Hardware implementation

dependent register 0 (HID0).”

Critical interrupt enable

0 Critical input and watchdog timer interrupts are disabled.

1 Critical input and watchdog timer interrupts are enabled.

—

Preserved.

External interrupt enable

0 External input, decrementer, and fixed-interval timer interrupts are disabled.

1 External input, decrementer, and fixed-interval timer interrupts are enabled.

Problem state.

0 The processor is in supervisor mode, can execute any instruction, and can access

any resource (for example, GPRs, all SPRs, and the MSR).

1 The processor is in user mode, cannot execute any privileged instruction, and

cannot access any privileged resource.

Floating-point available.

0 Floating-point unit is unavailable. The processor cannot execute floating-point

instructions, including floating-point loads, stores, and moves. (An FP unavailable

interrupt is generated on attempted execution of floating-point instructions).

1 Floating-point unit is available. The processor can execute floating-point

instructions. (Note that for the

e200z3, the floating-point unit is not supported; an

unimplemented operation exception is generated for attempted execution of

floating-point instructions when FP is set).

Machine check enable.

0 Machine check interrupts are disabled. Checkstop mode is entered when the

p_mcp_b input is recognized asserted or an ISI or ITLB exception occurs on a fetch

of the first instruction of an exception handler.

1 Machine check interrupts are enabled.

FE0

Floating-point exception mode 0 (not used by the e200z3).

—

Reserved, should be cleared.

Debug interrupt enable.

0 Debug interrupts are disabled.

1 Debug interrupts are enabled if DBCR0[IDM] is set.

FE1

Floating-point exception mode 1 (not used by the e200z3)

Table 7.

MSR field descriptions (continued)

Bits

Name

Description

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