UM0434 datasheet(40/390 Pages) STMICROELECTRONICS

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UM0434

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Data exception address register (DEAR). After most data storage interrupts

(DSIs), or on an alignment interrupt or data TLB interrupt, DEAR is set to the

effective address (EA) generated by the faulting instruction.

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SPRG0–SPRG7, USPRG0. For software use. See

Section 4.10: Software use

SPRs (SPRG0–SPRG7 and USPRG0) on page 63,” for details on these registers.

The e200z3 does not allow user-mode access to the SPRG3 register. Book E

defines access to SPRG3 as implementation-dependent.

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Exception syndrome register (ESR). A syndrome to differentiate between the

different kinds of exceptions that can generate the same interrupt.

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Interrupt vector prefix register (IVPR) and interrupt-specific interrupt vector offset

registers (IVORs). Provide the address of the interrupt handler for different classes

of interrupts.

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Save/restore register 0 (SRR0). Saves machine state on a non-critical interrupt

and contains the address of the instruction at which execution resumes when an

rfi instruction executes at the end of a non-critical-class interrupt handler routine.

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Save/restore register 1 (SRR1). Saves machine state from the MSR on non-critical

interrupts and restores machine state when rfi executes.

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Critical save/restore register 0 (CSRR0). Saves machine state on a critical

interrupt and contains the address of the instruction at which execution resumes

when an rfci instruction executes at the end of a critical-class interrupt handler

routine.

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Critical save/restore register 1 (CSRR1). Saves machine state from the MSR on

critical interrupts and restores machine state when rfci executes.

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Debug facility registers

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Debug control registers (DBCR0–DBCR2). Provide control for enabling and

configuring debug events.

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Debug status register (DBSR). Contains debug event status.

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Instruction address compare registers (IAC1–IAC4). Contain addresses and/or

masks to specify instruction address compare debug events.

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Data address compare registers (DAC1–DAC2). Contain addresses and/or masks

to specify data address compare debug events.

Note:

The e200z3 does not implement data value compare registers (DVC1 and DVC2).

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Timer registers

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Time base (TB). Maintains the time of day and operates interval timers. The TB

consists of two 32-bit registers, time base upper (TBU) and time base lower (TBL).

Only supervisor level software can write to the time base registers, but both user

and supervisor level software can read them.

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Decrementer register (DEC). A 32-bit decrementing counter for causing a

decrementer exception after a programmable delay.

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Decrementer auto-reload (DECAR). Supports the auto-reload feature of the

decrementer.

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Timer control register (TCR). Controls the decrementer, fixed interval timer, and

watchdog timer options.

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Timer status register (TSR). Contains status on timer events and the most recent

watchdog-timer-initiated processor reset.

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