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UM0434

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MODE

Embedded floating-point operating mode.

0 Default hardware results operating mode. The

e200z3 supports only mode 0.

1 IEEE754 hardware results operating mode (not supported by the

e200z3).

Controls the operating mode of the embedded floating-point APU. Software should read the value

of this bit after writing it to determine whether the implementation supports the selected mode.

Implementations return the value written if the selected mode is supported. Otherwise, the value

read indicates the hardware-supported mode.

SOV

Summary integer overflow. Set when an instruction sets OV. SOV remains set until it is cleared by

an mtspr specifying SPEFSCR.

Integer overflow. Set whenever an integer or fractional SPE instruction signals an overflow in the

low element result.

Embedded floating-point guard bit. Used by the floating-point round exception handler. Cleared if

a floating-point data exception occurs for the low elements. Corresponds to the low element

result.

Embedded floating-point sticky bit. For use by the floating-point round exception handler. FX is

cleared if a floating-point data exception occurs for the low elements. FX corresponds to the low

element result.

FINV

Embedded floating-point invalid operation/input error. In mode 0, FINV is set if the A or B low

element operand of a floating-point instruction is Infinity, NaN, or Denorm, or if the operation is a

divide and the low element dividend and divisor are both 0. In mode 1, FINV is set on an IEEE754

invalid operation (IEEE754-1985 sec7.1) in the low element.

FDBZ

Embedded floating-point divide by zero. Set when a floating-point divide instruction executes with

a low element divisor of 0 and the low element dividend is a finite non-zero number.

FUNF

Embedded floating-point underflow. Set when the execution of a floating-point instruction results

in an underflow in the low element.

FOVF

Embedded floating-point overflow. Set when the execution of a floating-point instruction results in

an overflow in the low element.

—

Reserved, should be cleared.

FINXE

Embedded floating-point inexact exception enable. If the exception is enabled, a floating-point

round exception is taken under one of the following conditions:

For both elements, the result of a floating-point instruction does not result in overflow or

underflow, and the result for either element is inexact (FG | FX = 1.

FGH | FXH =1)

The result of a floating-point instruction does result in overflow (FOVF=1 or FOVFH=1) for either

element, but floating-point overflow exceptions are disabled (FOVFE=0)

The result of a floating-point instruction results in underflow (FUNF=1 or FUNFH=1), but floating-

point underflow exceptions are disabled (FUNFE=0), and no floating-point data exception occurs.

0 Exception disabled.

1 Exception enabled.

FINVE

Embedded floating-point invalid operation/input error exception enable.

0 Exception disabled.

1 Exception enabled. A floating-point data exception is taken if FINV or FINVH is set by a floating-

point instruction.

Table 22.

SPEFSCR field descriptions (continued)

Bits

Name

Description

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