UM0434 datasheet(29/390 Pages) STMICROELECTRONICS

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e200z3 core complex overview

UM0434

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3.5.2

Interrupt classes

All interrupts may be categorized as asynchronous/synchronous and critical/noncritical.

●

Asynchronous interrupts (such as machine check, critical input, and external interrupts)

are caused by events that are independent of instruction execution. For asynchronous

interrupts, the address reported in a save/restore register is the address of the

instruction that would have executed next had the asynchronous interrupt not occurred.

●

Synchronous interrupts are those that are caused directly by the execution or

attempted execution of instructions. Synchronous inputs are further divided into precise

and imprecise types.

–

Synchronous precise interrupts are those that precisely indicate the address of the

instruction causing the exception that generated the interrupt or, in some cases,

the address of the immediately following instruction. The interrupt type and status

bits allow determination of which of the two instructions has been addressed in the

appropriate save/restore register.

–

Synchronous imprecise interrupts are those that may indicate the address of the

instruction causing the exception that generated the interrupt, or some instruction

after the instruction causing the interrupt. If the interrupt was caused by either the

context synchronizing mechanism or the execution synchronizing mechanism, the

address in the appropriate save/restore register is the address of the interrupt-

forcing instruction. If the interrupt was not caused by either of those mechanisms,

the address in the save/restore register is the last instruction to start execution and

may not have completed. No instruction following the instruction in the

save/restore register has executed.

3.5.3

Interrupt types

The e200z3 core processes all interrupts as either debug, critical, or noncritical types.

Separate control and status register sets are provided for each type of interrupt. The core

handles interrupts from these three categories in the following order of priority:

Debug interrupt—The EIS defines a separate set of resources for the debug interrupt.

The debug save and restore registers (DSRR0/DSRR1) are used to save state when a

debug interrupt is taken; the rfdi instruction restores state when interrupt handling

completes.The debug enable bit, HID0[DAPUEN], determines what interrupt is taken

when a debug exception occurs, as follows:

–

If DAPUEN = 0, the debug interrupt is disabled. Debug interrupts use the critical

interrupt resources: CSRR0/CSRR1 and rfci; rfdi is treated as an illegal

instruction. DCLREE, DCLRCE, CICLRDE, and MCCLRDE settings are ignored

and are assumed to be ones.

–

If DAPUEN = 1, the debug APU is enabled. Debug interrupts use DSRR0/DSRR1

for saving state, and rfdi is available for returning from a debug interrupt.

Noncritical interrupts—First-level interrupts that allow the processor to change program

flow to handle conditions generated by external signals, errors, or unusual conditions

arising from program execution or from programmable timer events. These interrupts

are largely identical to those defined by the OEA portion of the PowerPC architecture.

They use the save and restore registers (SRR0/SRR1) to save state when they are

taken, and they use the rfi instruction to restore state. Asynchronous noncritical

interrupts can be masked by the external interrupt enable bit, MSR[EE].

Critical interrupts—Critical interrupts can be taken during a noncritical interrupt or

during regular program flow. They use the critical save and restore registers

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