UM0434 datasheet(28/390 Pages) STMICROELECTRONICS

28 / 390 page

UM0434

e200z3 core complex overview

29/391

3.4

VLE APU

This section describes the extensions to the Book E instructions to support the PowerPC

VLE APU.

●

rfci, rfdi, rfi do not mask bit 62 of CSRR0, DSRR0, or SRR0. The destination address

is [D,C]SRR0[32–62] || 0b0.

●

bclr, bclrl, bcctr, bcctrl do not mask bit 62 of the LR or CTR. The destination address

is [LR, CTR][32–62] || 0b0.

3.5

Interrupts and exception handling

The core supports an extended exception handling model, with nested interrupt capability

and extensive interrupt vector programmability. The following sections define the interrupt

model, including an overview of interrupt handling as implemented on the e200z3 core, a

brief description of the interrupt classes, and an overview of the registers involved in the

processes.

3.5.1

Interrupt handling

In general, interrupt processing begins with an exception that occurs due to external

conditions, errors, or program execution problems. When an exception occurs, the

processor checks whether interrupt processing is enabled for that particular exception. If

enabled, the interrupt causes the state of the processor to be saved in the appropriate

registers and prepares to begin execution of the handler located at the associated vector

address for that particular exception.

Once the handler is executing, the implementation may need to check bits in the exception

syndrome register (ESR), the machine check syndrome register (MCSR), or the signal

processing and embedded floating-point status and control register (SPEFSCR), depending

on the exception type, to verify the specific cause of the exception and take appropriate

action.

The core complex supports the interrupts described in

Section 3.5.4.

Floating-Point Negative Absolute Value

efsnabs

evfsnabs

rD,rA

Floating-Point Subtract

efssub

evfssub

rD,rA,rB

Floating-Point Test Equal

efststeq

evfststeq

crD,rA,rB

Floating-Point Test Greater Than

efststgt

evfststgt

crD,rA,rB

Floating-Point Test Less Than

efststlt

evfststlt

crD,rA,rB

Floating-Point Single-Precision Multiply-Add

efsmadd

evfsmadd

rD,rA,rB

Floating-Point Single-Precision Negative Multiply-Add

efsnmadd

evfsnmadd

rD,rA,rB

Floating-Point Single-Precision Multiply-Subtract

efsmsub

evfsmsub

rD,rA,rB

Floating-Point Single-Precision Negative Multiply-Subtract

efsnmsub

evfsnmsub

rD,rA,rB

Table 3.

Scalar and vector embedded floating-point APU instructions (continued)

Instruction

Mnemonic

Syntax

Scalar

Vector

UM0434 датащи(PDF) 28 Page - STMicroelectronics

UM0434 датащи(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL