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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UM0434 датащи(PDF) 97 Page - STMicroelectronics |
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UM0434 датащи(HTML) 97 Page - STMicroelectronics |
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97 / 390 page  Register model UM0434 98/391 accessible in user mode, an illegal exception is generated. If the invalid SPR is accessible only in supervisor mode and the CPU core is in supervisor mode (MSR[PR] = 0), an illegal exception is generated. If the invalid SPR address is accessible only in supervisor mode and the CPU is not in supervisor mode (MSR[PR] = 1), a privilege exception is generated. 4.18.2 Synchronization requirements for SPRs Except for the following registers, no synchronization is required for accessing SPRs beyond those stated in Book E. EREF completely describes synchronization requirements. Software requirements for synchronization before/after accessing these registers are shown in Table 88. The notation CSI in the table refers to context synchronizing instructions, including sc, isync, rfi, rfci, and rfdi. Table 87. System response to invalid SPR reference SPR address bit 5 Mode MSR[PR] Response 0 — — Illegal exception 1 Supervisor 0 Illegal exception 1 User 1 Privilege exception Table 88. Additional synchronization requirements for SPRs Context altering event or instruction Required before Required after Notes mtmsr[UCLE] None CSI mfspr DBCNT Debug counter register msync None (1) DBSR Debug status register msync None HID0 Hardware implementation dependent register 0 None None HID1 Hardware implementation dependent register 1 msync None MMUCSR MMU control and status register 0 CSI None mtspr BUCSR Branch unit control and status register None CSI CTXCR Context control register CSI CSI DBCNT Debug counter register None CSI (1) DBCR0 Debug control register 0 None CSI DBCR1 Debug control register 1 None CSI DBCR2 Debug control register 2 None CSI DBCR3 Debug control register 3 None CSI DBSR Debug status register msync None HID0 Hardware implementation dependent reg 0 CSI CSI MMUCSR MMU control and status register 0 CSI CSI 1. Not required if counter is not currently enabled. |
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