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UM0434 датащи(PDF) 73 Page - STMicroelectronics |
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UM0434 датащи(HTML) 73 Page - STMicroelectronics |
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73 / 390 page ![]() Register model UM0434 74/391 Debug control register 1 (DBCR1) DBCR1, shown in Table 52, is used to configure instruction address compare operation. Table 53 describes debug control register 1 fields. Table 52. Debug control register 1 (DBCR1) 32 33 34 35 36 37 38 39 40 41 42 47 48 49 50 51 52 53 54 55 56 57 58 63 Field IAC1USIAC1ERIAC2USIAC2ERIAC12M — IAC3USIAC3ERIAC4USIAC4ERIAC34M — Reset All zeros R/W R/W SPR SPR 309 Table 53. DBCR1 field descriptions Bits Name Description 32–33 IAC1US Instruction address compare 1 user/supervisor mode. 00 AC1 debug events are not affected by MSR[PR]. 01 Reserved. 10 AC1 debug events can occur only if MSR[PR] = 0 (supervisor mode). 11 AC1 debug events can occur only if MSR[PR] = 1 (user mode). 34–35 IAC1ER Instruction address compare 1 effective/real mode. 00 AC1 debug events are based on effective address. 01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 AC1 debug events are based on effective address and can occur only if MSR[IS] = 0. 11 AC1 debug events are based on effective address and can occur only if MSR[IS] = 1. 36–37 IAC2US Instruction address compare 2 user/supervisor mode. 00 AC2 debug events are not affected by MSR[PR]. 01 Reserved. 10 AC2 debug events can occur only if MSR[PR] = 0 (supervisor mode). 11 AC2 debug events can occur only if MSR[PR] = 1 (user mode). 38–39 IAC2ER Instruction address compare 2 effective/real mode. 00 AC2 debug events are based on effective address. 01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 AC2 debug events are based on effective address and can occur only if MSR[IS] = 0. 11 AC2 debug events are based on effective address and can occur only if MSR[IS] = 1. |
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