UM0434 datasheet(69/390 Pages) STMICROELECTRONICS

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UM0434

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A debug event can be enabled when there is an attempt to execute an instruction from an

address in one of the following contexts:

●

In an IAC

●

Inside or outside a range specified by IAC1 and IAC2

●

Inside or outside a range specified by IAC3 and IAC4

●

To blocks of addresses specified by the combination of the IAC1 and IAC2

●

To blocks of addresses specified by the combination of the IAC3 and IAC4.

Because all instruction addresses must be word-aligned, the two low-order bits of the IACs

are reserved and do not participate in the comparison with the instruction address.

Data address compare registers (DAC1–DAC2)

The data address compare 1 register (DAC1) and data address compare 2 register (DAC2),

shown in

Table 48, are each 32 bits. A debug event can be enabled by loads, stores, or

cache operations to an address specified in either DAC1 or DAC2, inside or outside a range

specified by the DAC1 and DAC2, or blocks of addresses specified by the combination of the

DAC1 and DAC2.

The contents of DAC1 or DAC2 are compared to the address generated by a data access

instruction.

4.12.2

Debug counter register (DBCNT)

The debug counter register (DBCNT) contains two 16-bit counters (CNT1 and CNT2) that

can be configured to operate independently or concatenated into a single 32-bit counter.

Each counter can be configured to count down (decrement) when one or more count-

enabled events occur. The counters operate regardless of whether counters are enabled to

generate debug exceptions. When a count value reaches zero, a debug count event is

signaled and a debug event can be generated (if enabled). Upon reaching zero, the counter

is frozen. A debug counter signals an event on the transition from a value of one to a final

value of zero. Loading a value of zero into the counter prevents the counter from counting.

The debug counter is configured by the contents of DBCR3. DBCNT is shown in

Table 49.

Table 48.

Data address compare registers (DAC1–DAC2)

Field

Data address

Reset

All zeros

R/W

SPR

SPR 316 (DAC1); SPR 317 (DAC2)

Table 49.

DBCNT register

47 48

Field

CNT1

CNT2

Reset

Undefined on

m_por assertion, unchanged on p_reset_b assertion

R/W

SPR

SPR 562

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