UM0434 datasheet(30/390 Pages) STMICROELECTRONICS

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UM0434

e200z3 core complex overview

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(CSRR0/CSRR1) to save state when they are taken, and they use the rfci instruction to

restore state. These interrupts can be masked by the critical enable bit, MSR[CE].

Book E defines the critical input, watchdog timer, and machine check interrupts as

critical interrupts, but the e200z3 core defines a third set of resources for the debug

interrupt, as described in

Table 4.

All interrupts except debug interrupts are ordered within the two categories of noncritical

and critical, such that only one interrupt of each category is reported, and when it is

processed (taken), no program state is lost. Because save/restore register pairs are serially

reusable, program state may be lost when an unordered interrupt is taken.

3.5.4

Interrupt registers

Table 4.

Interrupt registers

Description

Noncritical interrupt registers

SRR0

Save/restore register 0—Stores the address of the instruction causing the exception or

the address of the instruction that will execute after the rfi instruction.

SRR1

Save/restore register 1—Saves machine state on noncritical interrupts and restores

machine state after an rfi instruction is executed.

Critical interrupt registers

CSRR0

Critical save/restore register 0—On critical interrupts, stores either the address of the

instruction causing the exception or the address of the instruction that executes after the

rfci.

CSRR1

Critical save/restore register 1—Saves machine state on critical interrupts and restores

machine state after an rfci instruction is executed.

Debug interrupt registers

DSRR0

Debug save/restore register 0—Used to store the address of the instruction that will

execute after an rfdi instruction is executed.

DSRR1

Debug save/restore register 1—Stores machine state on debug interrupts and restores

machine state after an rfdi instruction is executed.

Syndrome registers

MCSR

Machine check syndrome register—Saves machine check syndrome information on

machine check interrupts.

ESR

Exception syndrome register—Provides a syndrome to differentiate among the different

kinds of exceptions that generate the same interrupt type. Upon generation of a specific

exception type, the associated bits are set and all other bits are cleared.

SPE APU interrupt registers

SPEFSCR

Signal processing and embedded floating-point status and control register—Provides

interrupt control and status as well as various condition bits associated with the

operations performed by the SPE APU.

Other interrupt registers

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