UM0434 datasheet(37/390 Pages) STMICROELECTRONICS

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UM0434

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This chapter describes the registers of the e200z3 core. It includes an overview of registers

defined by the Book E architecture, highlighting differences in how these registers are

implemented in the e200z3 core, and it describes the e200z3-specific registers in detail. Full

descriptions of the architecture-defined register set are provided in the

EREF.

The Book E architecture defines register-to-register operations for all computational

instructions. Source data for these instructions is accessed from the on-chip registers or as

immediate values embedded in the opcode. The three-register instruction format allows

specification of a target register distinct from the two source registers, thus preserving the

original data for use by other instructions. Data is transferred between memory and registers

with explicit load and store instructions only.

The e200z3 extends the general-purpose registers (GPRs) to 64 bits to support SPE APU

operations. PowerPC Book E instructions operate on the lower 32 bits of the GPRs only, and

the upper 32 bits are unaffected by these instructions. SPE vector instructions operate on

the entire 64-bit register. The SPE APU defines load and store instructions for transferring

64-bit values to/from memory.

Figure 3 shows the complete e200z3 register set, indicating which registers are accessible

in supervisor mode and which in user mode. The number to the left of the special-purpose

registers (SPRs) is the decimal number used in the instruction syntax to access the register.

For example, the integer exception register (XER) is SPR 1.

GPRs are accessed through instruction operands. Access to other registers can be explicit,

using instructions such as Move to Special-Purpose Register (mtspr) and Move from

Special-Purpose Register (mfspr), or implicit as part of the execution of an instruction.

Some registers are accessed both explicitly and implicitly.

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