82374EB datasheet(75/208 Pages) INTEL

75 / 208 page

82374EB82374SB

If a counter is programmed to readwrite two-byte counts the following precaution applies A program must

not transfer control between writing the first and second byte to another routine which also writes into that

same counter Otherwise the counter will be loaded with an incorrect count The count must always be

completely loaded with both bytes

Bits 6 and 7 are also used to select the counter for the control word you are writing

Following reset the control words for each register are undefined You must program each timer to bring it into

a known state However each counter OUT signal is reset to 0 following reset The SPKR output interrupt

controller input IRQ0 (internal) bit 5 of port 061h and the internally generated Refresh request are each reset

to 0 following reset

Bit

Description

Counter Select

The Counter Selection bits select the counter the control word acts upon as shown

below The Read Back Command is selected when bits 76 are both 1

Bit 76

Function

Counter 0 select

Counter 1 select

Counter 2 select

Read Back Command (see Section 332)

ReadWrite Select

Bits 54 are the readwrite control bits The Counter Latch Command is selected

when bits 54 are both 0 The readwrite options include readwrite least significant byte readwrite

most significant byte or readwrite the LSB and then the MSB The actual counter programming is

done through the counter IO port (040h 041h and 042h for counters 0 1 and 2 respectively)

Bit 54

Function

Counter Latch Command (see Section 333)

RW Least Significant Byte (LSB)

RW Most Significant Byte (MSB)

RW LSB then MSB

Counter Mode Selection

Bits 31 select one of six possible modes of operation for the counter as

shown below Note that for the fail safe timer (timer 2 counter 0) modes 1 2 3 4 and 5 are reserved

Bit 31

Mode

Function

000

Out signal on end of count (e0)

001

Hardware retriggerable one-shot (Reserved for timer 2 counter 0)

X10

Rate generator (divide by n counter) (Reserved for timer 2 counter 0)

X11

Square wave output (Reserved for timer 2 counter 0)

100

Software triggered strobe (Reserved for timer 2 counter 0)

101

Hardware triggered strobe (Reserved for timer 2 counter 0)

BinaryBCD Countdown Select

When bit 0e0 a binary countdown is used The largest possible

binary count is 216 When bit 0e1 a binary coded decimal (BCD) count is used The largest BCD

count allowed is 104

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