82374EB datasheet(22/208 Pages) INTEL

22 / 208 page

82374EB82374SB

Pin Name

Type

Description

M16

MEMORY CHIP SELECT 16

M16

is an input when the ESC component owns the

ISA bus M16

is an output when an external ISA bus Master owns the ISA bus The

ISA slave memory drives this signal Low if it is a 16-bit memory device For ISA to EISA

translation cycles the ESC combinatorially asserts M16

if either EX32

or EX16

are asserted This signal has an external pull-up resistor

IO16

16 BIT IO CHIP SELECT

IO16

signal is used to indicate a 16-bit IO bus cycle This

signal is asserted by the IO devices to indicate that they support 16-bit IO bus cycles

All IO accesses to the ESC registers are run as 8-bit IO bus cycles This signal has

an external pull-up resistor

MRDC

MEMORY READ

MRDC

signal indicates a read cycle to the ISA memory devices

MRDC

is the command to a memory slave that it may drive data onto the ISA data

bus MRDC

is an output when the ESC owns the ISA bus MRDC

is an input when

an external ISA Bus master owns the ISA Bus This signal is driven by the ESC during

refresh cycles

MWTC

MEMORY WRITE

MWTC

signal indicates a write cycle to the ISA memory devices

MWTC

is the command to a memory slave that it may latch data from the ISA data

bus MWTC

is an output when the ESC owns the ISA bus MWTC

is an input when

an ISA Bus master owns the ISA Bus

SMRDC

out

SYSTEM MEMORY READ

SMRDC

signal is asserted by the ESC to request a

memory slave to drive data onto the data lines SMRDC

indicates that the memory

read cycle is for an address below the 1 MByte range on the ISA bus This signal is also

asserted during refresh cycles

SMWTC

out

SYSTEM MEMORY WRITE

SMWTC

signal is asserted by the ESC to request a

memory slave to accept data from the data lines SMWTC

indicates that the memory

write cycle is for an address below the 1 MByte range

IORC

IO READ

IORC

is the command to an ISA IO slave device that it may drive data on

to the data bus (SD 150 ) The device must hold the data valid until after IORC

negated IORC

is an output when the ESC component owns the ISA bus IORC

an input when an ISA Bus master owns the ISA Bus

IOWC

IO WRITE

IOWC

is the command to an ISA IO slave device that it may latch data

from the ISA data bus (SD 150 ) IOWC

is an output when the ESC component owns

the ISA Bus IOWC

is an input when an ISA Bus master owns the ISA Bus

CHRDY

IO CHANNEL READY

CHRDY when asserted allows ISA Bus resources request

additional time (wait-states) to complete the cycle CHRDY is an input when the ESC

owns the ISA Bus CHRDY is an input to the ESC during compatible DMA cycles

CHRDY is an output during ISA Bus master cycles to PCI slave or ESC internal register

The ESC will ignores CHRDY for ISA-Bus master accessing an ISA-Bus slave

IOCHK

IO CHANNEL CHECK

IOCHK

can be asserted by any resource on the ISA Bus

When asserted it indicates that a parity or an uncorrectable error has occurred for a

device or memory on the ISA Bus A NMI will be generated to the CPU if enabled

82374EB датащи(PDF) 22 Page - Intel Corporation

82374EB датащи(HTML) 22 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL