82374EB datasheet(71/208 Pages) INTEL

71 / 208 page

82374EB82374SB

3222 SCAGASTSCATTER-GATHER STATUS REGISTER

Channels 0

0419hChannels 1

041AhChannels 2

041BhChannels 3

041DhChannels 5

041EhChannels 6

041FhChannels 7

Default Value

08h

Attribute

Read Only Relocatable

Size

8 Bits

The Scatter-Gather Status Register provides Scatter-Gather process status information to the CPU or Master

An active bit is set to 1 after the S-G Start command is issued The active bit will be 0 before the initial start

command following a terminal count and after an S-G Stop command is issued The Current Buffer and Base

Buffer State Bits indicate whether the corresponding register has a buffer loaded It is possible for the Base

Buffer State to be set while the Current Buffer State is cleared When the Current Buffer transfer is complete

the Base Buffer will not be moved into the Current Buffer until the start of the next data transfer Thus the

Current Buffer State is empty (cleared) while the Base Buffer State is full (set) The Terminate bit is set active

after a Stop command after TC for the last buffer in the list and both Base and Current buffers have expired

The EOP and IRQ13 Bits indicate which end of process indicator will be used to alert the system of an S-G

process termination The EOL status bit is set if DMA controller has loaded the last buffer of the Link List

Bit

Description

Next Link Null Indicator

If the Next SGD fetched from memory during a fetch operation has the EOL

value (1) the current value of the Next Link register is not overwritten Instead bit 7 of the channel’s

S-G Status register the Next Link Null indicator is set to a 1 If the fetch returns a EOL value not equal

to (1) this bit is reset to 0 This status bit is written after every fetch operation Following reset or

Master Clear this bit is reset to 0 This bit is also cleared by an S-G Start Command Write

Reserved

IRQ13 or EOP on Last Buffer

When the IRQ13EOP status bit is 1 EOP was either defaulted to at

reset or selected through the S-G Command register as the S-G process termination indicator EOP

will be issued to alert the system when a terminal count occurs or following the Stop Command When

this bit is returned as a 0 an IRQ13 will be issued to alert the CPU of this same status

Reserved

S-G Base Buffer State

When the Base Buffer status bit contains a 0 the Base Buffer is empty When

the Base Buffer Status bit is set to 1 the Base buffer has a buffer link loaded Note that the Base

Buffer State may be set while the Current buffer state is cleared This condition occurs when the

Current Buffer expires following a transfer the Base Buffer will not be moved into the Current Register

until the start of the next DMA transfer

S-G Current Buffer State

When the Current Buffer status bit contains a 0 the Current Buffer is

empty When the Current Buffer status bit is set to 1 the Current Buffer has a buffer link loaded and is

considered full Following reset bit 2 is reset to 0

Reserved

82374EB датащи(PDF) 71 Page - Intel Corporation

82374EB датащи(HTML) 71 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL