82374EB datasheet(7/208 Pages) INTEL

7 / 208 page

CONTENTS

PAGE

353 PORT 92 REGISTER

354 LEISAMGLAST EISA BUS MASTER GRANTED REGISTER

36 Power Management Registers

361 APMCADVANCED POWER MANAGEMENT CONTROL PORT

362 APMSADVANCED POWER MANAGEMENT STATUS PORT

37 APIC Registers

371 IOREGSELIO REGISTER SELECT REGISTER

372 IOWINIO WINDOW REGISTER

373 APICIDIO APIC IDENTIFICATION REGISTER

374 APICIDIO APIC IDENTIFICATION REGISTER

375 APICARBIO APIC ARBITRATION REGISTER

376 IOREDTBL 150

IO REDIRECTION TABLE REGISTERS

40 ADDRESS DECODING

41 BIOS Memory Space

42 IO Addresses Contained Within The ESC

101

43 Configuration Addresses

110

44 X-Bus Peripherals

112

45 IO APIC Registers

114

50 EISA CONTROLLER FUNCTIONAL DESCRIPTION

115

51 Overview

115

52 Clock Generation

116

521 CLOCK STRETCHING

116

53 EISA Master Cycles

117

531 EISA MASTER TO 32-BIT EISA SLAVE

117

532 EISA MASTER TO 16-BIT ISA SLAVE

119

533 EISA MASTER TO 8-BIT EISAISA SLAVES

119

534 EISA MASTER BACK-OFF

120

54 ISA Master Cycles

121

541 ISA MASTER TO 32-16-BIT EISA SLAVE

121

542 ISA MASTER TO 16-BIT ISA SLAVE

121

543 ISA MASTER TO 8-BIT EISAISA SLAVE

123

544 ISA WAIT STATE GENERATION

123

55 Mis-Match Cycles

124

56 Data Swap Buffer Control Logic

125

57 Servicing DMA Cycles

126

58 Refresh Cycles

126

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