82374EB datasheet(29/208 Pages) INTEL

29 / 208 page

82374EB82374SB

2102 PCEB BUFFER COHERENCY CONTROL

Pin Name

Type

Description

NMFLUSH

NEW MASTER FLUSH

NMFLUSH

is a bi-directional signal which is used to

provide handshake between PCEB and ESC to control flushing of system buffers on

behalf of EISA masters

During an EISA bus ownership change before ESC can grant the bus to the EISA

master (or DMA) it must ensure that system buffers are flushed and buffers pointing

(potentially) towards EISA subsystem are disabled The ESC asserts NMFLUSH

signal for one PCI clock indicating the request for system buffer flushing (After

driving NMFLUSH

asserted for 1 PCI clock the ESC tri-states NMFLUSH

signal)

When PCEB samples NMFLUSH

asserted it starts immediately to drive

NMFLUSH

asserted and initiates internal and external requests for buffer flushing

After all buffers have been flushed (indicated by the proper handshake signals) the

PCEB negates NMFLUSH

for 1 PCI clock and stops driving it When the ESC

samples the signal deasserted that indicates that all system buffers are flushed it

grants EISA bus to an EISA master (or DMA) The ESC resumes responsibility of

default NMFLUSH

driver and starts driving NMFLUSH

deasserted until the next

time a new EISA master (or DMA) wins arbitration

This signal is synchronous with PCICLK and is negated by the ESC at reset

AFLUSH

APIC FLUSH

AFLUSH

is bi-directional signal between the PCEB and ESC that

controls system buffer flushing on behalf of the APIC After a reset the ESC negates

AFLUSH

until the APIC is initialized and the first interrupt request is recognized

SDCPYUP

out

SYSTEM (DATA) COPY UP

SDCPYUP is used to control the direction of the byte

copy operation A High on the signal indicates a COPY UP operation where the

lower byte lower word of the SD data bus is copied on to the higher byte or higher

word of the bus A Low on the signal indicates a COPY DOWN operation where the

higher byte(s) of the data bus are copied on to the lower byte(s) of the bus The

PCEB uses the signal to perform the actual data byte copy operation during mis-

matched cycles

SDOE 20

out

SYSTEM DATA OUTPUT ENABLES

SDOE

enable the SD data output of the

PCEB Data Swap Buffers on to EISA bus The ESC activates these signals only

during mis-matched cycles The PCEB uses these signal to enable the SD data

buffers as follows

SDOE0

Enables byte lane 0 SD 70

SDOE1

Enables byte lane 1 SD 158

SDOE2

Enables byte lane 2 SD 2316 and byte lane 3 SD 3124

SDLE 30

out

SYSTEM DATA LATCH ENABLES

SDLE 30

enable the latching of EISA data

bus These signals are activated only during mis-matched cycles except PCEB

initiated write cycle The PCEB uses these signals to latch the SD data bus as

follows

SDLE0

Latch byte lane 0 SD 70

SDLE1

Latch byte lane 0 SD 158

SDLE2

Latch byte lane 0 SD 2316

SDLE3

Latch byte lane 0 SD 3124

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