82374EB datasheet(63/208 Pages) INTEL

63 / 208 page

82374EB82374SB

3210 DMA BASE AND CURRENT HIGH BYTEWORD COUNT REGISTER DMA BASE HIGH BYTE

WORD COUNT REGISTER

401hDMA Channel 0

403hDMA Channel 1

405hDMA Channel 2

407hDMA Channel 3

4C6hDMA Channel 5

4CAhDMA Channel 6

4CEhDMA Channel 7

Default Value

00h

Attribute

ReadWrite

Size

8 Bits per channel

Each channel has a 8-bit Current High ByteWord Count register This register provides the uppermost 8 bits

for the number of transfers to be performed The byteword count is decremented after each transfer The

intermediate value of the byteword count is stored in the register during the transfer When the value in the

Following the end of a DMA service it may also be re-initialized by an autoinitialization back to its original value

autoinitialize can occur only when a TC occurs If it is not autoinitialized this register will have a count of

FFFFh after TC

The High ByteWord Count register must be the last ByteWord Count register programmed Writing to the

8237 Compatible ByteWord Count registers will clear the High ByteWord Count register to 00h

When the Extended Mode register is programmed for ‘‘count by word’’ transfers tofrom a 16-bit IO with

shifted address the ByteWord count will indicate the number of 16-bit words to be transferred

When the Extended Mode register is programmed for ‘‘count by byte’’ transfers the ByteWord Count will

indicate the number of bytes to be transferred The number of bytes does not need to be a multiple of the

transfer size in this case

Each channel has a Base High ByteWord Count register located at the same port address as the correspond-

ing Current High ByteWord Count register These registers store the original value of their associated Current

registers During autoinitialize these values are used to restore the Current registers to their original values

Normally the Base registers are written simultaneously with their corresponding Current register in successive

8 bit bytes by the microprocessor However in Chaining Mode only the Base register set is programmed and

the Current register is not effected The Base registers cannot be read by any external agents

In Scatter-Gather mode these registers store the lowest 8 bits of the current High ByteWord Count During a

Scatter-Gather transfer the DMA will load a reserve buffer into the base High ByteWord Count register

In Chaining Mode these register store the lowest 8 bits of the current High ByteWord Count The CPU will

then program the base register set with a reserve buffer

Bit

Description

Base and Current High ByteWord Count

These bits represent the 8 high order byteword count

bits used when counting down a DMA transfer Upon reset or Master Clear the value of these bits is

00h

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