82374EB datasheet(95/208 Pages) INTEL

95 / 208 page

82374EB82374SB

375 APICARBIO APIC ARBITRATION REGISTER

Address Offset

02h

Default Value

000F0011h

Attribute

Read Only

Size

32 Bits

The APICARB Register contains the bus arbitration priority for the IO APIC This register is loaded whenever

the IO APIC ID Register is written

Bit

Description

3128

Reserved

2724

IO APIC Identification

This 4 bit field contains the IO APIC identification

230

Reserved

376 IOREDTBL 150

IO REDIRECTION TABLE REGISTERS

Address Offset

10-11h (IOREDTBL0)

12-13h (IOREDTBL1)

14-15h (IOREDTBL2)

16-17h (IOREDTBL3)

18-19h (IOREDTBL4)

1A-1Bh (IOREDTBL5)

1C-1Dh (IOREDTBL6)

1E-1Fh (IOREDTBL7)

20-21h (IOREDTBL8)

22-23h (IOREDTBL9)

24-25h (IOREDTBL10)

26-27h (IOREDTBL11)

28-29h (IOREDTBL12)

2A-2Bh (IOREDTBL13)

2C-2Dh (IOREDTBL14)

2E-2Fh (IOREDTBL15)

Default Value

xx000000 00010xxxh

Attribute

ReadWrite Read Only

Size

64 Bits each

There are 16 IO Redirection Table entry registers Each register is a dedicated entry for each interrupt input

pin Unlike IRQ pins of the 8259A the notion of interrupt priority is completely unrelated to the position of the

physical interrupt input pin on the APIC Instead software determines the vector (and therefore the priority) for

each corresponding interrupt input pin For each interrupt pin the operating system can also specify the signal

polarity (low active or high active) whether the interrupt is signaled as edges or levels as well as the destina-

tion and delivery mode of the interrupt The information in the redirection table is used to translate the

corresponding interrupt pin information into an inter-APIC message

For a signal on an edge-sensitive interrupt input pin to be recognized as a valid edge (and not a glitch) the

input level on the pin must remain asserted until the IO APIC Unit broadcasts the corresponding message

over the APIC bus and the message has been accepted by the destination(s) specified in the destination field

Only then will the source APIC be able to recognize a new edge on that Interrupt Input pin That new edge only

results in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt

Request Register bit to go from 0 to 1 (In other words if the interrupt wasn’t already pending at the destina-

tion)

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