82374EB datasheet(13/208 Pages) INTEL

13 / 208 page

82374EB82374SB

PCI Bus

The PCI Bus has been defined to address the growing industry needs for a standardized

local bus that is not

directly dependent on the speed and the size of the processor bus New generations of personal computer

system software such as WindowsTM and Win-NTTM with sophisticated graphical interfaces multi-tasking and

multi-threading bring new requirements that traditional PC IO architectures can not satisfy In addition to the

higher bandwidth reliability and robustness of the IO subsystem is becoming increasingly important The PCI

environment addresses these needs and provides an upgrade path for the future PCI features include

Processor independent

Multiplexed burst mode operation

Synchronous at frequencies from 20–33 MHz

120 MBytesec usable throughput (132 MBytesec peak) for 32 bit data path

240 MBytesec usable throughput (264 MBytesec peak) for 64 bit data path

Optional 64 bit data path with operations that are transparent with the 32 bit data path

Low latency random access (60 ns write access latency to slave registers from a master parked on the bus)

Capable of full concurrency with processormemory subsystem

Full multi-master capability allowing any PCI master peer-to-peer access to any PCI slave

Hidden (overlapped) central arbitration

Low pin count for cost effective component packaging (addressdata multiplexed)

Address and data parity

Three physical address spaces memory IO and configuration

Comprehensive support for autoconfiguration through a defined set of standard configuration functions

System partitioning shown in Figure 1 illustrates how the PCI can be used as a common interface between

different portions of a system platform that are typically supplied by the chip set vendor These portions are the

HostPCI Bridge (including a main memory DRAM controller and an optional second level cache controller)

and the PCI-EISA Bridge Thus the PCI allows a system IO core design to be decoupled from the processor

memory treadmill enabling the IO core to provide maximum benefit over multiple generations of processor

memory technology For this reason the PCI-EISA Bridge can be used with different processors Regardless

of the new requirements imposed on the processor side of the HostPCI Bridge (eg 64-bit data path 33V

interface etc) the PCI side remains unchanged which allows reusability not only of the rest of the platform

chip set (ie PCI-EISA Bridge) but also of all other IO functions interfaced at the PCI level These functions

typically include graphics SCSI and LAN

EISA Bus

The EISA bus in the system shown in the Figure 10 represents a second level IO bus It allows personal

computer platforms built around the PCI as a primary IO bus to leverage the large EISAISA product base

Combinations of PCI and EISA buses both of which can be used to provide expansion functions will satisfy

even the most demanding applications

Along with compatibility with 16-bit and 8-bit ISA hardware and software the EISA bus provides the following

key features

32-bit addressing and 32-bit data path

33 MBytesec bus bandwidth

Multiple bus master support through efficient arbitration

Support for autoconfiguration

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