82374EB datasheet(61/208 Pages) INTEL

61 / 208 page

82374EB82374SB

328 DBCADMA BASE AND CURRENT ADDRESS REGISTER (8237 COMPATIBLE SEGMENT)

000hDMA Channel 0

002hDMA Channel 1

004hDMA Channel 2

006hDMA Channel 3

0C0hDMA Channel 4

0C4hDMA Channel 5

0C8hDMA Channel 6

0CChDMA Channel 7

Default Value

0000h

Attribute

ReadWrite

Size

16 Bits per channel

Each channel has a 16-bit Current Address register This register holds the value of the 16 least significant bits

of the full 32-bit address used during DMA transfers The address is automatically incremented or decrement-

ed after each transfer and the intermediate values of the address are stored in the Current Address register

during the transfer This register is written to or read from by the microprocessor or bus master in successive

8-bit bytes The programmer must issue the ‘‘Clear Byte Pointer Flip-Flop’’ command to reset the internal byte

pointer and correctly align the write prior to programming the Current address register After clearing the Byte

Pointer Flip-flop the first write to the Current Address port programs the low byte bits 70

and the second

write programs the high byte bits 158

This procedure applies for read cycles also It may also be re-initial-

ized by an autoinitialize back to its original value autoinitialize takes place only after a TC or EOP

Each channel has a Base Address register located at the same port address as the corresponding Current

Address register These registers store the original value of their associated Current registers During autoini-

tialize these values are used to restore the Current registers to their original values The Base registers are

written simultaneously with their corresponding Current register in successive 8-bit bytes by the microproces-

sor The Base registers cannot be read by any external agents

In Scatter-Gather Mode these registers store the lowest 16-bits of the current memory address During a

Scatter-Gather transfer the DMA will load a reserve buffer into the base memory address register

In Chaining Mode these register store the lowest 16-bits of the current memory address The CPU will program

the base register set with a reserve buffer

Bit

Description

150

Base and Current Address

These bits represent the 16 least significant address bits used during

DMA transfers Together with the DMA Low Page register they help form the ISA-compatible 24-bit

DMA address As an extension of the ISA compatible functionality the DMA High Page register

completes the 32-bit address needed when implementing ESC extensions such as DMA to the PCI

bus slaves that can take advantage of full 32-bit addressability Upon reset or Master Clear the value

of these bits is 0000h

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