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82374EB датащи(PDF) 47 Page - Intel Corporation

номер детали 82374EB
подробное описание детали  SYSTEM COMPONENT (ESC)
PDF  208 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

82374EB датащи(HTML) 47 Page - Intel Corporation

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82374EB82374SB
3117 PACPCIAPIC CONTROL REGISTER
Address Offset
70h
Default Value
00h
Attribute
ReadWrite
Size
8 Bits
The PAC Register controls the operation of the INTR signal in APICPIC configuration and the routing of the
System Management Interrupt (SMI)
Bit
Description
72
Reserved
1
SMI Routing Control (SMIRC)
When SMIRCe1 the SMI is routed via the APIC When SMIRCe0
the SMI is routed via the SMI
signal Note that when SMRCe1 INTR can not be routed through the
APIC since it is sharing the APIC interrupt input with SMI
0
INTR Routing Control (INTRC)
When APIC is enabled (in mixed or pure APIC mode) this bit allows
the ESC’s external INTR signal to be masked (forces INTR to the inactive state but does not tri-states
the signal) Thus the CPU’s INTR pin can be used (by providing a simple -gate) for the APIC Local
Interrupt (LINTRx) However INTR must not be masked via this bit when APIC is disabled and INTR is
the only mechanism to signal the 8259 recognized interrupts to the CPU When INTRCe1 INTR is
disabled (APIC must be enabled) When INTRCe0 INTR is enabled
3118 TESTCTEST CONTROL REGISTER
Address Offset
88h
Default Value
00h
Attribute
ReadWrite
Size
8 Bits
This register provides control for ESC manufacturing test modes The functionality of this register is reserved
3119 SMICNTLSMI CONTROL REGISTER
Address Offset
A0h
Default Value
08h
Attribute
ReadWrite
Size
8 Bits
For the 82374SB the SMICNTL Register provides Fast Off Timer control STPCLK
enabledisable and CPU
clock scaling This register also enablesdisables the system management interrupt (SMI)
Bit
Description
7
Reserved Must be 0 when writing this register
64
Reserved
3
Fast Off Timer Freeze (CTMRFRZ)
This field enablesdisables the Fast Off Timer When this bit is 1
the Fast Off timer stops counting This prevents time-outs from occurring while executing SMM code
When this bit is 0 the Fast Off timer counts
47



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