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82374EB датащи(PDF) 25 Page - Intel Corporation

номер детали 82374EB
подробное описание детали  SYSTEM COMPONENT (ESC)
PDF  208 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

82374EB датащи(HTML) 25 Page - Intel Corporation

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82374EB82374SB
25 EISA Arbitration Signals
Pin Name
Type
Description
MREQ 30
in
MASTER REQUEST
MREQ 30
are slot specific signals used by EISA bus
masters to request bus access MREQ
once asserted must remain asserted
until the corresponding MACK
is asserted The MREQ
is negated on the falling
edge of BCLK slightly before the end of a master transfer The LA
BE
MIO
and WR
lines should be floated on or before the rising edge of BCLK
after MREQ
is negated The end of the last bus cycle is derived from CMD
in
this case The MREQ
signals are asserted on the falling edge of BCLK MREQ
is always sampled on the rising edge of BCLK MREQ
is synchronous with
respect to BCLK After asserting MREQ
the corresponding master must not
assert MREQ
until 15 BCLKs after CMD
is negated
MREQ 74
in
MASTER REQUESTPCI INTERRUPT REQUEST
These pins behave in one of
two modes depending on the state of the Mode Select Register bit 1 and bit 0
PIRQ 03
Master Request
MREQ
lines are slot specific signals used by EISA bus masters
to request bus access This signal behave in the same manner as MREQ 30
signals
PCI Interrupt Request
PIRQ
are used to generate asynchronous interrupts to
the CPU via the Programmable Interrupt Controller (82C59) integrated in the ESC
These signals are defined as level sensitive and are asserted low The PIRQx
can be shared with PC compatible interrupts IRQ3IRQ7 IRQ9IRQ15 The
PIRQx
Route Control Register determines which PCI interrupt is shared with
which PC compatible interrupt
Register
Pins
Bit 10
MREQ7
MREQ6
MREQ5
MREQ4
PIRQ0
PIRQ1
PIRQ2
PIRQ3
00
PIRQ0
PIRQ1
PIRQ2
PIRQ3
01
PIRQ0
PIRQ1
MREQ5
MREQ4
10
PIRQ0
MREQ6
MREQ5
MREQ4
11
MREQ7
MREQ6
MREQ5
MREQ4
25



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