82374EB datasheet(48/208 Pages) INTEL

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82374EB82374SB

Pin Name

Description

STPCLK

Scaling Enable (CSTPCLKSC)

This bit enablesdisables control of the STPCLK

highlow times by the clock scaling timers When bit 2e1 the STPCLK

signal scaling control

is enabled When enabled (and bit 1e1 enabling the STPCLK

signal) the high and low times

for the STPCLK

signal are controlled by the Clock Scaling STPCLK

High Timer and Clock

Scaling STPCLK

Low Timer Registers respectively When bit 2e0 (default) the scaling

control of the STPCLK

signal is disabled

STPCLK

Signal Enable (CSTPCLKE)

This bit permits software to place the CPU into a low

power state When bit 1e1 the STPCLK

signal is enabled and a read from the APMC

to be asserted When bit 1e0 (default) the STPCLK

signal is

disabled and is negated (high) Software can set this bit to 0 by writinga0toitorbyany write to

the APMC Register

SMI

Gate (CSMIGATE)

When bit 0e1 the SMI

signal is enabled and a system

management interrupt condition causes the SMI

signal to be asserted When bit 0e0

(default) the SMI

signal is masked and negated This bit only affects the SMI

signal and

does not effect the detectionrecording of SMI events (ie This bit does not effect the SMI

status bits in the SMIREQ Register) Thus SMI conditions can be pending when this bit is set to

1 If an SMI is pending when this bit is set to 1 the SMI

signal is asserted

3120 SMIENSMI ENABLE REGISTER

Address Offset

A2-A3h

Default Value

0000h

Attribute

ReadWrite

Size

16 Bits

For the 82374SB his register enables the generation of SMI (asserting the SMI

signal) for the associated

hardware events (bits 50 ) and software events (bit 7) When a hardware event is enabled the occurrence of

a corresponding event results in the assertion of SMI

if enabled via the SMICNTL Register The SMI

asserted independent of the current power state (Power-On or Fast Off) The default for all sources in this

Bit

Description

158

Reserved

APMC Write SMI Enable

This bit enables SMI for writes to the APMC Register When bit 7e1

writes to the APMC Register generate an SMI When bit 7e0 writes to the APMC Register do not

generate an SMI

EXTSMI

SMI Enable

When bit 6e1 asserting the EXTSMI

input signal generates an SMI When

bit 6e0 asserting EXTSMI

does not generate an SMI

Fast Off Timer SMI Enable

This bit enables the Fast Off Timer to generate an SMI When bit 5e1

the timer generates an SMI when it decrements to zero When bit 5e0 the timer does not generate

an SMI

IRQ12 SMI Enable (PS2 Mouse Interrupt)

This bit enables the IRQ12 signal to generate an SMI

When bit 4e1 asserting the IRQ12 input signal generates an SMI When bit 4e0 asserting IRQ12

does not generate an SMI

IRQ8 SMI Enable (RTC Alarm Interrupt)

This bit enables the IRQ8 signal to generate an SMI

When bit 3e1 asserting the IRQ8 input signal generates an SMI When bit 3e0 asserting IRQ8

does not generate an SMI

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