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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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82374EB датащи(PDF) 68 Page - Intel Corporation |
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82374EB датащи(HTML) 68 Page - Intel Corporation |
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68 / 208 page  82374EB82374SB 3218 CHAINSTACHAINING MODE STATUS REGISTER Register Location 04D4h Default Value 00h Attribute Read Only Size 8 Bits This register is read only and is used to determine if chaining mode for a particular channel is enabled or disabled A 1 read in this register indicates that the channel’s chaining mode is enabled A 0 indicates that the chaining mode is disabled All Chaining mode bits are disabled after a reset with reset After the DMA is used in Chaining mode the CPU will need to clear the Chaining mode enable bit if non-Chaining mode is desired Bit Description 75 Chaining Mode Status If this bit is set to 1 then this channel has chaining enabled by writing 1 to bit 2 of the Chaining Mode Register This bit can be reset to 0 by either writinga0tobit2ofthe Chaining 30 Mode Register or reset being asserted or by a Master Clear Command 4 Reserved 3219 CHINTSTCHANNEL INTERRUPT STATUS REGISTER Register Location 040Ah Default Value 00h Attribute Read Only Size 8 Bits Channel Interrupt Status is a read only register and is used to indicate the source (channel) of a DMA chaining interrupt on IRQ13 The DMA controller asserts IRQ13 after reaching terminal count with chaining mode enabled It does not assert IRQ13 during the initial programming sequence that loads the Base registers After a reset a read of this register will produce 00h Bit Description 75 Chaining Interrupt Status When a channel interrupt status read returns a 0 bits 7530 indicates that channel did not assert IRQ13 When a channel interrupt status read returns a 1 then that channel 30 asserted IRQ13 after reaching a Terminal Count 4 Reserved 3220 CHAINBECCHAIN BUFFER EXPIRATION CONTROL REGISTER Register Location 040Ch Default Value 00h Attribute Read Only Size 8 Bits This register is read only and reflects the outcome of the expiration of a chain buffer A Chain Buffer Expiration Control register bit with 0 indicates the DMA controller asserts IRQ13 when the DMA controller reaches terminal count A 1 indicates the DMA controller asserts TC when the DMA controller reaches terminal count This bit is programmed in bit 4 of the Chaining Mode register 68 |
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