82374EB datasheet(27/208 Pages) INTEL

27 / 208 page

82374EB82374SB

27 Interrupt Controller Signals

Pin Name

Type

Description

IRQ 159

INTERRUPT REQUEST

IRQ These signals provide both system board components

and EISA bus IO devices with a mechanism for asynchronously interrupting the CPU

IRQ8

The assertion mode of each interrupt can be programmed to be edge or level

IRQ 731

triggered An asserted IRQ input must remain asserted until after the falling edge of

INTA

If the input is negated before this time a DEFAULT IRQ7 will occur when the

CPU acknowledges the interrupt

IRQ8

requires an external pull-up resistor (8 KX –10 KX)

INTR

out

CPU INTERRUPT

INTR is driven by the ESC to signal the CPU that an Interrupt

request is pending and needs to be serviced It is asynchronous with respect to BCLK

or PCICLK and it is always an output The interrupt controllers must be programmed

following a reset to ensure that this pin takes on a known state Upon reset the state of

this pin is undefined

NMI

out

NON-MASKABLE INTERRUPT

NMI is used to force a non-maskable interrupt to the

CPU The CPU registers an NMI when it detects a rising edge on NMI NMI will remain

active until a read from the CPU to the NMI register at port 061h is detected by the

ESC This signal is set to low upon reset

28 APIC Bus Signals

Pin Name

Type

Description

APICCLK

APIC BUS CLOCK

APICCLK provides the timing reference for the APIC Bus

Changes on APICD 10

are synchronous to the rising edge of APICCLK

APICD 10

APIC DATA

APICD1 and APICD0 are the APIC data bus signals Interrupt messages

are sentreceived over this bus APIC arbitration uses APICD1

29 System Power Management Signals (82374SB Only)

Pin Name

Type

Description

STPCLK

out

STOP CLOCK

STPCLK

is asserted by the ESC in response to one of many

maskable hardware or software events For 33V processors that are not 5V tolerant

STPCLK

is driven to the CPU STPCLK

pin through a 5V to 33V translator When

the CPU samples STPCLK

asserted it responds by stopping its internal clock After a

hard reset this signal is negated

SMI

out

SYSTEM MANAGEMENT INTERRUPT

SMI

is asserted by the ESC in response to

one of many maskable hardware or software events For 33V processors that are not

5V tolerant SMI

is driven to the CPU SMI

pin through a 5V to 33V translator The

CPU recognizes the falling edge of SMI

as the highest priority interrupt in the system

The CPU responds by entering SMM (System Management Mode) SMI

is negated

during and following reset After a hard reset this signal is negated

82374EB датащи(PDF) 27 Page - Intel Corporation

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