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82374EB датащи(PDF) 59 Page - Intel Corporation |
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82374EB датащи(HTML) 59 Page - Intel Corporation |
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59 / 208 page ![]() 82374EB82374SB Bit Description 73 Reserved Must be 0 2 DMA Channel Mask SetClear Writinga1tobit2 sets the mask bit and disables the incoming DREQ for the selected channel Writinga0tobit2 clears the mask bit and enables the incoming DREQ for the elected channel 10 DMA Channel Select Bits 10 select the DMA Channel Mode Register to program with bit 2 Bits 10 Channel 00 Channel 0 (4) 01 Channel 1 (5) 10 Channel 2 (6) 11 Channel 3 (7) 326 WAMBWRITE ALL MASK BITS REGISTER Register Location 0FhChannels 0-3 0DEhChannels 4-7 Default Value 0Fh Attribute ReadWrite Size 8 Bits This command allows enabling and disabling of incoming DREQ assertions by writing the mask bits for each controller DMA1 or DMA2 simultaneously rather than by individual channel as is done with the ‘‘Write Single Mask Bit’’ command Two registers store the current mask status for DMA1 and DMA2 Setting the mask bit disables the incoming DREQ x for that channel Clearing the mask bit enables the incoming DREQ x Unlike the ‘‘Write Single Mask Bit’’ command this command includes a status read to check the current mask status of the selected DMA channel group When read the mask register current status appears on bits 30 A channel’s mask bit is automatically set when the Current Word Count register reaches terminal count (unless the channel is programmed for autoinitialization) The entire register is also set by a reset or a Master Clear Setting the entire register disables all DMA requests until a clear Mask register instruction allows them to occur Two important points should be taken into consideration when programming the mask registers First individu- ally masking DMA Channel 4 (DMA controller 2 Channel 0) will automatically mask DMA Channels 30 as this channel group is logically cascaded onto Channel 4 Second masking off DMA controller 2 with a write to port 0DEh will also mask off DREQ assertions from DMA controller 1 for the same reason when DMA Channel 4 is masked so are DMA Channels 0-3 59 |
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