AD9523-1SLASHPCBZ datasheet(24/60 Pages) AD

24 / 60 page

AD9523-1

Rev. B | Page 24 of 60

Input 2× Frequency Multiplier

The 2× frequency multiplier provides the option to double the

frequency at the PLL2 input. This allows the user to take advantage

of a higher frequency at the input to the PLL (PFD) and, thus,

allows for reduced in-band phase noise and greater separation

between the frequency generated by the PLL and the modulation

spur associated with PFD. However, increased reference spur

separation results in harmonic spurs, introduced by the frequency

multiplier, that increase as the duty cycle deviates from 50% at the

OSC_IN inputs. As such, beneficial use of the frequency multiplier

is application-specific. Typically, a VCXO with proper interfacing

has a duty cycle that is approximately 50% at the OSC_IN inputs.

Note that the maximum output frequency of the 2× frequency

multipliers must not exceed the maximum PFD rate that is

specified in Table 11.

PLL2 Feedback Divider

PLL2 has a feedback divider (N divider) that enables it to provide

integer frequency up-conversion. The PLL2 N divider is a com-

bination of a prescaler (P) and two counters, A and B.

The total

divider value is

N = (P × B) + A

where P = 4.

The feedback divider is a dual modulus prescaler architecture, with

a nonprogrammable P that is equal to 4. The value of the B counter

can be from 3 to 63, and the value of the A counter can be from 0 to 3.

However, due to the architecture of the divider, there are constraints,

as listed in

Table 45.

PLL2 Loop Filter

The PLL2 loop filter requires the connection of an external

capacitor from LF2_EXT_CAP (Pin 11) to LDO_VCO (Pin 12),

as illustrated in Figure 27. The value of the external capacitor

depends on the operating mode and the desired phase noise

performance. For example, a loop bandwidth of approximately

500 kHz produces the lowest integrated jitter. A lower bandwidth

produces lower phase noise at 1 MHz but increases the total

integrated jitter.

Table 20. PLL2 Loop Filter Programmable Values

RZERO

(Ω)

CPOLE1

(pF)

RPOLE2

(Ω)

CPOLE2

(pF)

LF2_EXT_CAP1

(pF)

3250

900

Fixed at 16

Typical at 1000

3000

450

2750

300

2500

225

2250

2100

2000

1850

1 External loop filter capacitor.

VCO Divider M1 and VCO Divider M2

The VCO dividers provide frequency division between the internal

VCO and the clock distribution. Each VCO divider can be set to

divide by 3, 4, or 5. When the AD9523-1 is used without any

zero delay feedback (internal or external), the phase relationship

between the reference inputs and the outputs is a function of

the phase relationship between the OSC input and the reference

inputs. Because the VCO divider is not reset by SYNC, there is

an additional phase variability of up to x VCO periods, where

x = VCO divider setting.

VCO Calibration

The AD9523-1 on-chip VCO must be manually calibrated to

ensure proper operation over process and temperature. This is

accomplished by setting the calibrate VCO bit (Register 0x0F3,

Bit 1) to 1. (This bit is not self-clearing.) The setting can be

performed as part of the initial setup before executing the

IO_Update bit (Register 0x234, Bit 0 = 1). A readback bit, VCO

calibration in progress (Register 0x22D, Bit 0), indicates when

a VCO calibration is in progress by returning a logic true (that is,

Bit 0 = 1). If the EEPROM is in use, setting the calibrate VCO bit

to 1 before saving the register settings to the EEPROM ensures

that the VCO calibrates automatically after the EEPROM has

loaded. After calibration, it is recommended that a sync be initiated

(see the Clock Distribution Synchronization section).

Note that the calibrate VCO bit defaults to 0. This bit must

change from 0 to 1 to initiate a calibration sequence. Therefore,

any subsequent calibrations require the following sequence:

VCO calibration is controlled by a calibration controller that

runs off the VCXO input clock. The calibration requires that

PLL2 be set up properly to lock the PLL2 loop and that the

VCXO clock be present.

During power-up or reset, the distribution section is automatically

held in sync until the first VCO calibration is finished. Therefore,

no outputs can occur until VCO calibration is complete and PLL2

is locked.

Initiate a VCO calibration under the following conditions:

•

After changing any of the PLL2 B counter and A counter

settings or after a change in the PLL2 reference clock

frequency. This means that a VCO calibration should be

initiated any time that a PLL2 register or reference clock

changes such that a different VCO frequency is the result.

•

Whenever system calibration is desired. The VCO is designed

to operate properly over extremes of temperature even

when it is first calibrated at the opposite extreme. However,

a VCO calibration can be initiated at any time, if desired.

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