AD9523-1SLASHPCBZ datasheet(6/60 Pages) AD

6 / 60 page

AD9523-1

Rev. B | Page 6 of 60

REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE

Input Frequency Range

400

MHz

Input Slew Rate (OSC_IN)

400

V/μs

Minimum limit imposed for jitter

performance

Common-Mode Internally

Generated Input Voltage

0.6

0.7

0.8

Input Common-Mode Range

1.025

1.475

For dc-coupled LVDS (maximum swing)

Differential Input Voltage,

Sensitivity Frequency < 250 MHz

100

mV p-p

Capacitive coupling required; can

accommodate single-ended input

by ac grounding of unused input;

instantaneous voltage on either pin

must not exceed the 1.8 V dc supply rails

Differential Input Voltage,

Sensitivity Frequency > 250 MHz

200

mV p-p

Capacitive coupling required; can

accommodate single-ended input

by ac grounding of unused input;

instantaneous voltage on either pin

must not exceed the 1.8 V dc supply rails

Differential Input Resistance

4.8

kΩ

Differential Input Capacitance

Duty Cycle

Duty cycle limits are set by pulse width

high and pulse width low

Pulse Width Low

Pulse Width High

CMOS MODE, SINGLE-ENDED INPUT

Input Frequency Range

250

MHz

Input High Voltage

2.0

Input Low Voltage

0.8

Input Capacitance

Duty Cycle

Duty cycle limits are set by pulse width

high and pulse width low

Pulse Width Low

1.6

Pulse Width High

1.6

OSC_CTRL OUTPUT CHARACTERISTICS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT VOLTAGE

High

VDD3_PLL − 0.15

RLOAD > 20 kΩ

Low

150

REF_TEST INPUT CHARACTERISTICS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REF_TEST INPUT

Input Frequency Range

250

MHz

Input High Voltage

2.0

Input Low Voltage

0.8

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