AD9523-1SLASHPCBZ datasheet(52/60 Pages) AD

52 / 60 page

AD9523-1

Rev. B | Page 52 of 60

Address

Bits

Bit Name

Description

0x191

[7:0]

Channel divider,

Bits[7:0] (LSB)

Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1

is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).

[7:2]

Divider phase

Divider initial phase after a sync is asserted relative to the divider input clock (from the

VCO divider output). LSB = ½ of a period of the divider input clock.

Phase = 0: no phase offset.

Phase = 1: ½ period offset, …

Phase = 63: 31.5 period offset.

0x192

[1:0]

Channel divider, Bits[9:8] (MSB)

10-bit channel divider, Bits[9:8] (MSB).

Table 52. PLL1 Output Control (PLL1_OUT, Pin 72)

Address

Bits

Bit Name

Description

[7:5]

CLK2 select[2:0]

Bits[2:0] of the VCO divider channel select.

Bit 7 selects Channel Output 6.

Bit 6 selects Channel Output 5.

Bit 5 selects Channel Output 4.

0: VCO Divider M1.

1: VCO Divider M2.

PLL1 output CMOS driver

strength

CMOS driver strength.

1: weak.

0: strong.

0x1BA

[3:0]

PLL1 output divider

0000: divide-by-1.

0001: divide-by-2 (default).

0010: divide-by-4.

0100: divide-by-8.

1000: divide-by-16.

No other inputs permitted.

Table 53. PLL1 Output Channel Control

Address

Bits

Bit Name

Description

PLL1 output driver power-down

PLL1 output driver power-down.

[6:4]

CLK2 select[5:3]

Bits[5:3] of the VCO divider channel select.

Bit 6 selects Channel Output 9.

Bit 5 selects Channel Output 8.

Bit 4 selects Channel Output 7.

0: VCO Divider M1.

1: VCO Divider M2.

Route VCXO clock to

Channel 3 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input.

0: channel uses VCO divider output clock.

Route VCXO clock to

Channel 2 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input.

0: channel uses VCO divider output clock.

Route VCXO clock to

Channel 1 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input.

0: channel uses VCO divider output clock.

0x1BB

Route VCXO clock to

Channel 0 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input.

0: channel uses VCO divider output clock.

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