AD9523-1SLASHPCBZ datasheet(3/60 Pages) AD

3 / 60 page

AD9523-1

Rev. B | Page 3 of 60

SPECIFICATIONS

fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 2949.12 MHz, doubler is on, unless otherwise noted.

Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD and

TA (−40°C to +85°C) variation, as listed in Table 1.

CONDITIONS

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

VDD3_PLL, Supply Voltage for PLL1 and PLL2

3.135

3.3

3.465

3.3 V ± 5%

VDD3_VCO, Supply Voltage for VCO

3.135

3.3

3.465

3.3 V ± 5%

VDD3_REF, Supply Voltage Clock Output Drivers Reference

3.135

3.3

3.465

3.3 V ± 5%

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

3.135

3.3

3.465

3.3 V ± 5%

VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers

1.768

1.8

1.832

1.8 V ± 5%

TEMPERATURE RANGE, TA

−40

+25

+85

°C

1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,

respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).

SUPPLY CURRENT

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS

VDD3_PLL, Supply Voltage for PLL1 and PLL2

41.9

Decreases by 9 mA typical if REFB is turned off

VDD3_VCO, Supply Voltage for VCO and VCO Divider M1

75.8

All outputs use VCO Divider M1

VDD3_REF, Supply Voltage Clock Output Drivers Reference

VCO Divider M1 Enabled

LVPECL Mode, LVDS Mode

5.1

Use VCO Divider M1; only one output driver

is turned on; for each additional output that

is turned on, the current increments by 1.2 mA

maximum

HSTL Mode, CMOS Mode

3.6

Use VCO Divider M1; values are independent

of the number of outputs turned on

VCO Divider M2 Enabled

LVPECL Mode, LVDS Mode

30.1

Use VCO Divider M2; only one output driver

is turned on; for each additional output that

is turned on, the current increments by 1.2 mA

maximum

HSTL Mode, CMOS Mode

24.5

28.6

Use VCO Divider M2; values are independent

of the number of outputs turned on

VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers

3.2

5.8

Current for each divider: f = 122.88 MHz

VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers

6.4

Current for each divider: f = 983.04 MHz

CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF

Channel x control register, Bit 4 = 0

LVDS Mode, 7 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

11.5

13.2

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

f = 983.04 MHz

LVDS Mode, 3.5 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

6.5

7.5

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

26.3

f = 983.04 MHz

LVPECL Mode

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

14.4

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

46.5

f = 983.04 MHz

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