AD9523-1SLASHPCBZ datasheet(51/60 Pages) AD

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AD9523-1

Rev. B | Page 51 of 60

Table 50. PLL2 R2 Divider

Address

Bits

Bit Name

Description

0x0F7

[7:5]

Reserved

Reserved.

[4:0]

PLL2 R2 divider

Divide-by-1 to divide-by-31.

00000, 00001: divide-by-1.

Clock Distribution (Register 0x190 to Register 0x1B9)

Table 51. Channel 0 to Channel 13 Control (This Same Map Applies to All 14 Channels)

Address

Bits

Bit Name

Description

Invert divider output

Inverts the polarity of the divider’s output clock.

Ignore sync

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Power down channel

1: powers down the entire channel.

0: normal operation.

Lower power mode

(differential modes only)

Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This

reduction may result in power savings but at the expense of performance. Note that

this bit does not affect output swing and current, just the internal driver power.

1: low strength/lower power.

0: normal operation.

Driver mode.

Bit 3

Bit 2

Bit 1

Bit 0

Driver Mode

Tristate output

LVPECL (8 mA)

LVDS (3.5 mA)

LVDS (7 mA)

HSTL-0 (16 mA)

HSTL-1 (8 mA)

CMOS (both outputs in phase)

+ Pin: true phase relative to divider output

− Pin: true phase relative to divider output

CMOS (opposite phases on outputs)

+ Pin: true phase relative to divider output

− Pin: complement phase relative to divider output

CMOS

+ Pin: true phase relative to divider output

− Pin: high-Z

CMOS

+ Pin: high-Z

− Pin: true phase relative to divider output

CMOS

+ Pin: high-Z

− Pin: high-Z

CMOS (both outputs in phase)

+ Pin: complement phase relative to divider output

− Pin: complement phase relative to divider output

CMOS (both outputs out of phase)

+ Pin: complement phase relative to divider output

− Pin: true phase relative to divider output

CMOS

+ Pin: complement phase relative to divider output

− Pin: high-Z

CMOS

+ Pin: high-Z

− Pin: complement phase relative to divider output

0x190

[3:0]

Driver mode

Tristate output

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