AD9523-1SLASHPCBZ datasheet(49/60 Pages) AD

49 / 60 page

AD9523-1

Rev. B | Page 49 of 60

Address

Bits

Output PLL (PLL2) (Address 0x0F0 to Address 0x0F7)

Table 44. PLL2 Charge Pump Control

Address

Bits

Bit Name

Description

0x0F0

[7:0]

PLL2 charge pump control

These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA

with a full-scale magnitude of ~900 μA.

Table 45. PLL2 Feedback N Divider Control

Address

Bits

Bit Name

Description

[7:6]

A counter

A counter word.

[5:0]

B counter

B counter word.

Feedback Divider Constraints

A Counter (Bits[7:6])

Table 46. PLL2 Control

Bit Name

Description

PLL2 lock detector power-down

Controls power-down of the PLL2 lock detector.

1: lock detector powered down.

0: lock detector active.

Reserved

Default = 0; value must remain 0.

Enable frequency doubler

Enables doubling of the PLL2 reference input frequency.

1: enabled.

0: disabled.

Enable SPI control of antibacklash

pulse width

Controls the functionality of Register 0x0F2, Bits[2:1].

0 (default): device automatically controls the antibacklash period.

1: antibacklash period defined by Register 0x0F2, Bits[2:1].

[3:2]

Antibacklash pulse width control

Controls the PFD antibacklash period of PLL2.

00 (default): minimum.

01: low.

10: high.

11: maximum.

These bits are ineffective unless Register 0x0F2, Bit 4 = 1.

0x0F2

[1:0]

PLL2 charge pump mode

Controls the mode of the PLL2 charge pump.

00: tristate.

01: pump up.

10: pump down.

11 (default): normal.

Table 47. VCO Control

Address

Bits

Bit Name

Description

[7:5]

Reserved

Reserved.

Force release of distribution sync

when PLL2 is unlocked

0 (default): distribution is held in sync (static) until the output PLL locks. Then it is

automatically released from sync with all dividers synchronized.

1: overrides the PLL2 lock detector state; forces release of the distribution from sync.

Treat reference as valid

0 (default): uses the PLL1 VCXO indicator to determine when the reference clock to

the PLL2 is valid.

1: treats the reference clock as valid even if PLL1 does not consider it to be valid.

Force VCO to midpoint frequency

Selects VCO control voltage functionality.

0 (default): normal VCO operation.

1: forces VCO control voltage to midscale.

Calibrate VCO (not autoclearing)

1: initiates VCO calibration (this is not an autoclearing bit).

0: resets the VCO calibration.

0x0F3

Reserved

Reserved.

B Counter (Bits[5:0])

Allowed N Division (4 × B + A)

A = 0

B = 3

A = 0 or A = 1

B = 4

16, 17

A = 0 to A = 2

B = 5

20, 21, 22

A = 0 to A = 2

B = 6

24, 25, 26

0x0F1

A = 0 to A = 3

B ≥ 7

28, 29 … continuous to 255

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