AD9523-1SLASHPCBZ datasheet(14/60 Pages) AD

14 / 60 page

AD9523-1

Rev. B | Page 14 of 60

No.

Mnemonic

Type1

Description

LF2_EXT_CAP

PLL2 External Loop Filter Capacitor Connection. Connect capacitor to this pin and the LDO_VCO pin.

LDO_VCO

P/O

2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 μF decoupling capacitor from

this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close

proximity to the device.

VDD3_VCO

3.3 V Supply for VCO and VCO M1 Divider.

LDO_DIV_M1

P/O

1.8 V LDO Regulator Decoupling Pin for VCO Divider M1. Connect a 0.47 μF decoupling capacitor

from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed

in close proximity to the device.

Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.

REF_SEL

Reference Input Select. This pin has an internal 40 kΩ pull-down resistor.

SYNC

Manual Synchronization. This pin initiates a manual synchronization and has an internal 40 kΩ pull-

up resistor.

VDD3_REF

3.3 V Supply for Output Clock Drivers Reference and VCO Divider M2.

RESET

Digital Input, Active Low. Resets internal logic to default states. This pin has an internal 40 kΩ pull-up

resistor.

Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.

SCLK/SCL

Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial program-

ming. This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.

SDIO/SDA

I/O

Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA).

SDO

Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There

is no internal pull-up/pull-down resistor on this pin.

REF_TEST

Test Input to PLL1 Phase Detector.

OUT13

Complementary Square Wave Clocking Output 13. This pin can be configured as one side of

a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

OUT13

Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/

LVDS/HSTL output or as a single-ended CMOS output.

VDD3_OUT[12:13]

3.3 V Supply for Output 12 and Output 13 Clock Drivers.

OUT12

Complementary Square Wave Clocking Output 12. This pin can be configured as one side of

a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

OUT12

Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/

LVDS/HSTL output or as a single-ended CMOS output.

VDD1.8_OUT[12:13]

1.8 V Supply for Output 12 and Output 13 Clock Dividers.

OUT11

Complementary Square Wave Clocking Output 11. This pin can be configured as one side of

a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

OUT11

Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/

LVDS/HSTL output or as a single-ended CMOS output.

VDD3_OUT[10:11]

3.3 V Supply for Output 10 and Output 11 Clock Drivers.

OUT10

Complementary Square Wave Clocking Output 10. This pin can be configured as one side of

a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

OUT10

Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/

LVDS/HSTL output or as a single-ended CMOS output.

VDD1.8_OUT[10:11]

1.8 V Supply for Output 10 and Output 11 Clock Dividers.

OUT9

Complementary Square Wave Clocking Output 9. This pin can be configured as one side of

a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

OUT9

Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/

LVDS/HSTL output or as a single-ended CMOS output.

VDD3_OUT[8:9]

3.3 V Supply for Output 8 and Output 9 Clock Drivers.

OUT8

Complementary Square Wave Clocking Output 8. This pin can be configured as one side of

a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

OUT8

Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/

LVDS/HSTL output or as a single-ended CMOS output.

VDD1.8_OUT[8:9]

1.8 V Supply for Output 8 and Output 9 Clock Dividers.

OUT7

Complementary Square Wave Clocking Output 7. This pin can be configured as one side of

a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

OUT7

Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/

LVDS/HSTL output or as a single-ended CMOS output.

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