AD9523-1SLASHPCBZ datasheet(30/60 Pages) AD

30 / 60 page

AD9523-1

Rev. B | Page 30 of 60

A repeated start (Sr) condition can be used in place of a stop

condition. Furthermore, a start or stop condition can occur at

any time; partially transferred bytes are discarded.

For an I2C data write transfer containing multiple data bytes,

the peripheral drives a no acknowledge for the data byte that

follows a write to Register 0x234, thereby ending the I2C transfer.

For an I2C data read transfer containing multiple data bytes,

the peripheral drives data bytes of 0x00 for subsequent reads that

follow a read from Register 0x234.

Data Transfer Format

Send byte format. The send byte protocol is used to set up the register address for subsequent commands.

Slave Address

RAM Address High Byte

RAM Address Low Byte

Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address.

Slave Address

RAM Address

High Byte

RAM Address

Low Byte

RAM

Data 0

RAM

Data 1

RAM

Data 2

Receive byte format. The receive byte protocol is used to read the data byte(s) from the RAM, starting from the current address.

Slave Address

RAM Data 0

RAM Data 1

RAM Data 2

Read byte format. The combined format of the send byte and the receive byte.

Slave

Address

RAM Address

High Byte

RAM Address

Low Byte

Slave

Address

RAM

Data 0

RAM

Data 1

RAM

Data 2

I²C Serial Port Timing

SDA

SCL

tFALL

tSET; DAT

tLOW

tRISE

tHLD; STR

tHLD; DAT

tHIGH

tFALL

tSET; STR

tHLD; STR

tSPIKE

tSET; STP

tRISE

tIDLE

Figure 37. I²C Serial Port Timing

Table 23. I2C Timing Definitions

Parameter

Description

fI2C

I²C clock frequency

tIDLE

Bus idle time between stop and start conditions

tHLD; STR

Hold time for repeated start condition

tSET; STR

Setup time for repeated start condition

tSET; STP

Setup time for stop condition

tHLD; DAT

Hold time for data

tSET; DAT

Setup time for data

tLOW

Duration of SCL clock low

tHIGH

Duration of SCL clock high

tRISE

SCL/SDA rise time

tFALL

SCL/SDA fall time

tSPIKE

Voltage spike pulse width that must be suppressed by the input filter

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