AD9523-1SLASHPCBZ datasheet(50/60 Pages) AD

50 / 60 page

AD9523-1

Rev. B | Page 50 of 60

Table 48. VCO Divider Control

Address

Bits

Bit Name

Description

Reserved

Reserved.

VCO Divider M2

power-down

1: powers down the divider.

0: normal operation.

Note that VCO Divider M2 connects to Output Channel 4 through Output Channel 9.

[5:4]

Bit 5

Bit 4

Divider Value

Divide-by-3

Divide-by-4

Divide-by-5

VCO Divider M2

Divide-by-3

Reserved

Reserved.

VCO Divider M1

power-down

1: powers down the divider.

0: normal operation.

Note that VCO Divider M1 connects to all output channels.

0x0F4

[1:0]

VCO Divider M1

Bit 1

Bit 0

Divider Value

Divide-by-3

Divide-by-4

Divide-by-5

Divide-by-3

Table 49. PLL2 Loop Filter Control

Address

Bits

Bit Name

Description

Bit 7

Bit 6

RPOLE2

(Ω)

900

450

300

[7:6]

Pole 2 resistor (RPOLE2)

225

Bit 5

Bit 4

Bit 3

RZERO

(Ω)

3250

2750

2250

2100

3000

2500

2000

[5:3]

Zero resistor (RZERO)

1850

Bit 2

Bit 1

Bit 0

CPOLE1

(pF)

0x0F5

[2:0]

Pole 1 capacitor (CPOLE1)

[7:1]

Reserved

Reserved.

0x0F6

Bypass internal RZERO

resistor

Bypasses the internal RZERO resistor (RZERO = 0 Ω). Requires the use of a series external zero

resistor. This bit is the MSB of the loop filter control register (Address 0x0F5 and Address 0x0F6).

AD9523-1/PCBZ датащи(PDF) 50 Page - Analog Devices

AD9523-1/PCBZ датащи(HTML) 50 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL