AD9523-1SLASHPCBZ datasheet(26/60 Pages) AD

26 / 60 page

AD9523-1

Rev. B | Page 26 of 60

Clock Distribution Synchronization

first sets and then clears the bit. The synchronization event is the

clearing operation (that is, the Logic 1 to Logic 0 transition of

the bit). The dividers are all automatically synchronized to each

other when PLL2 is ready. The dividers support programmable

phase offsets from 0 to 63 steps, in half periods of the input

clock (for example, the VCO divider output clock). The phase

offsets are incorporated into the dividers through a preset for the

first output clock period of each divider. Phase offsets are

supported only by programming the initial phase and divide

value and then issuing a sync to the distribution (automatically

at startup or manually, if desired).

A block diagram of the clock distribution synchronization

functionality is shown in Figure 29. The synchronization

sequence begins with the primary synchronization signal,

which ultimately results in delivery of a synchronization strobe

to the clock distribution logic.

As indicated, the primary synchronization signal originates

from one of the following sources:

•

Direct synchronization source via the sync dividers bit

(see Table 55, Register 0x232, Bit 0)

•

Device pin, SYNC (Pin 17)

In normal operation, the phase offsets are already programmed

through the EEPROM or the SPI/I2C port before the AD9523-1

starts to provide outputs. Although the user cannot adjust the

phase offsets while the dividers are operating, it is possible to

adjust the phase of all the outputs together without powering

down PLL1 and PLL2. This is accomplished by programming

the new phase offset, using Bits[7:2] in Register 0x192 (see

Table 51) and then issuing a divide sync signal by using the

SYNC pin or the sync dividers bit (Register 0x232, Bit 0).

An automatic synchronization of the divider is initiated the first

time that PLL2 locks after a power-up or reset event. Subsequent

lock/unlock events do not initiate a resynchronization of the

distribution dividers unless they are preceded by a power-down

or reset of the part.

Both sources of the primary synchronization signal are logic OR’d;

therefore, any one of them can synchronize the clock distribution

output at any time. When using the sync dividers bit, the user

FAN OUT

VCO OUTPUT DIVIDER

SYNC (PIN 17)

SYNC

SYNC DIVIDERS BIT

DIVIDER

DRIVER

OUTx

OUT

SYNC

PHASE

DIVIDE

Figure 29. Clock Distribution Synchronization Block Diagram

DIVIDE = 2, PHASE = 0

DIVIDE = 2, PHASE = 6

VCO DIVIDER OUTPUT CLOCK

SYNC

CONTROL

6 × 0.5 PERIODS

Figure 30. Clock Output Synchronization Timing Diagram

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