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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9523-1/PCBZ датащи(PDF) 42 Page - Analog Devices |
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AD9523-1/PCBZ датащи(HTML) 42 Page - Analog Devices |
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42 / 60 page  AD9523-1 Rev. B | Page 42 of 60 Addr (Hex) Register Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value (Hex) 0x1A2 Channel 6 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x00 0x1A3 10-bit channel divider[7:0] (LSB) 0x1F 0x1A4 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1A5 Channel 7 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x20 0x1A6 10-bit channel divider[7:0] (LSB) 0x1F 0x1A7 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1A8 Channel 8 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x00 0x1A9 10-bit channel divider[7:0] (LSB) 0x1F 0x1AA Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1AB Channel 9 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x20 0x1AC 10-bit channel divider[7:0] (LSB) 0x1F 0x1AD Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1AE Channel 10 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x00 0x1AF 10-bit channel divider[7:0] (LSB) 0x1F 0x1B0 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1B1 Channel 11 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x20 0x1B2 10-bit channel divider[7:0] (LSB) 0x1F 0x1B3 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1B4 Channel 12 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x00 0x1B5 10-bit channel divider[7:0] (LSB) 0x1F 0x1B6 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1B7 Channel 13 control Invert divider output Ignore sync Power down channel Lower power mode Driver mode 0x20 0x1B8 10-bit channel divider[7:0] (LSB) 0x1F 0x1B9 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1BA PLL1 output control CLK2 select[2:0] PLL1 output CMOS driver strength Out PLL1 output 0x00 0x1BB PLL1 output channel control PLL1 output driver power- down CLK2 select[5:3] Reserved Route VCXO clock to Ch 3 divider input Route VCXO clock to Ch 2 divider input Route VCXO clock to Ch 1 divider input Route VCXO clock to Ch 0 divider input 0x80 Readback 0x22C Readback 0 Status PLL2 reference clock Status PLL2 feedback clock Status VCXO Status REF_TEST Status REFB Status REFA Lock detect PLL2 Lock detect PLL1 0x22D Readback 1 Reserved Reserved Reserved Reserved Holdover active Selected reference (in auto mode) Reserved VCO calibration in progress 0x22E Readback 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x22F Readback 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved |
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