AD9523-1SLASHPCBZ datasheet(23/60 Pages) AD

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AD9523-1

Rev. B | Page 23 of 60

PLL1 Input Dividers

Each reference input feeds a dedicated reference divider block.

The input dividers provide division of the reference frequency

in integer steps from 1 to 1023. They provide the bulk of the

frequency prescaling that is necessary to reduce the reference

frequency to accommodate the bandwidth that is typically

desired for PLL1.

PLL1 Reference Switchover

The reference monitor verifies the presence/absence of the

prescaled REFA and REFB signals (that is, after division by the

input dividers). The status of the reference monitor guides the

activity of the switchover control logic. The AD9523-1 supports

automatic and manual PLL reference clock switching between

REFA (the REFA and REFA pins) and REFB (the REFB and

REFB pins). This feature supports networking and infrastructure

applications that require redundant references.

There are several configurable modes of reference switchover. The

manual switchover is achieved either via a programming register

setting or by using the REF_SEL pin. The automatic switchover

occurs when REFA disappears and there is a reference on REFB.

The reference automatic switchover can be set to work as follows:

•

Nonrevertive: stay on REFB. Switch from REFA to REFB

when REFA disappears, but do not switch back to REFA

if it reappears. If REFB disappears, then go back to REFA.

•

Revert to REFA. Switch from REFA to REFB when REFA

disappears. Return to REFA from REFB when REFA returns.

See Table 42 for the PLL1 miscellaneous control register bit

settings.

PLL1 Holdover

In the absence of both input references, the device enters hold-

over mode. Holdover is a secondary function that is provided

by PLL1. Because PLL1 has an external VCXO available as a

frequency source, it continues to operate in the absence of the

input reference signals. When the device switches to holdover,

the charge pump tristates. The device continues operating in this

mode until a reference signal becomes available. Then the device

exits holdover mode, and PLL1 resynchronizes with the active

reference. In addition to tristate, the charge pump can be forced

to VCC/2 during holdover (Register 0x01C, Bit 6; see Table 42).

COMPONENT BLOCKS—OUTPUT PLL (PLL2)

PLL2 General Description

The output PLL (referred to as PLL2) consists of an optional

input reference doubler, reference divider, phase-frequency

detector (PFD), a partially integrated analog loop filter (see

Figure 27), an integrated voltage-controlled oscillator (VCO),

and a feedback divider. The VCO produces a nominal 3.0 GHz

signal with an output divider that is capable of division ratios of

3, 4, and 5.

The PFD of the output PLL drives a charge pump that increases,

decreases, or holds constant the charge stored on the loop filter

capacitors (both internal and external). The stored charge results

in a voltage that sets the output frequency of the VCO. The

feedback loop of the PLL causes the VCO control voltage to

vary in a way that phase locks the PFD input signals.

The gain of PLL2 is proportional to the current delivered by

the charge pump. The loop filter bandwidth is chosen to reduce

noise contributions from PLL sources that could degrade phase

noise requirements.

The output PLL has a VCO with multiple bands spanning a range

of 2.94 GHz to 3.1 GHz. However, the actual operating frequency

within a particular band depends on the control voltage that

appears on the loop filter capacitor. The control voltage causes

the VCO output frequency to vary linearly within the selected

band. This frequency variability allows the control loop of the

output PLL to synchronize the VCO output signal with the

reference signal applied to the PFD. Typically, the device

automatically selects the appropriate band as part of its

calibration process (invoked via the VCO control register

at Address 0x0F3, shown in Table 47).

N DIVIDER

TO DIST/

RESYNC

×2

PLL1_OUT

LDO

PLL_1.8V

LDO_DIV_M1

VDD3_VCO

VDD3_REF

LDO_VCO

DIVIDE-BY-

1, 2, 4, 8, 16

DIVIDE-BY-

1, 2, 3...31

DIVIDE-BY-

3, 4, 5,

DIVIDE-BY-4

PRESCALER

A/B

COUNTERS

CHARGE PUMP

7 BITS, 3.5µA LSB

PFD

RZERO

RPOLE2

CPOLE1

CPOLE2

LF2_EXT_CAP

VDD3_PLL

PLL CORE

1.9V

TO DIST/

RESYNC

DIVIDE-BY-

3, 4, 5,

AD9523-1

Figure 27. Output PLL (PLL2) Block Diagram

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