ATtiny43U datasheet(121/182 Pages) ATMEL

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8048B–AVR–03/09

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

• When ADATE or ADEN is cleared.

• During conversion, minimum one ADC clock cycle after the trigger event.

• After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

16.6.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

• In Single Conversion mode, always select the channel before starting the conversion. The

channel selection may be changed one ADC clock cycle after writing one to ADSC. However,

the simplest method is to wait for the conversion to complete before changing the channel

selection.

• In Free Running mode, always select the channel before starting the first conversion. The

channel selection may be changed one ADC clock cycle after writing one to ADSC. However,

the simplest method is to wait for the first conversion to complete, and then change the

channel selection. Since the next conversion has already started automatically, the next

result will reflect the previous channel selection. Subsequent conversions will reflect the new

channel selection.

16.6.2

ADC Voltage Reference

The ADC reference voltage (V

REF) indicates the conversion range for the ADC. Single ended

channels that exceed V

REF will result in codes close to 0x3FF. VREF can be selected as either

CC, or internal 1.1V reference, or external AREF pin. The internal 1.1V reference is generated

from the internal bandgap reference (V

BG) through an internal amplifier.

The first ADC conversion result after switching reference voltage source may be inaccurate, and

the user is advised to discard this result.

16.7

ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode. This reduces

noise induced from the CPU core and other I/O peripherals. The noise canceler can be used

with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure

should be used:

• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must

be selected and the ADC conversion complete interrupt must be enabled.

• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the

CPU has been halted.

• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake

up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt

wakes up the CPU before the ADC conversion is complete, that interrupt will be executed,

and an ADC Conversion Complete interrupt request will be generated when the ADC

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