LPC2921 datasheet(15/83 Pages) NXP

15 / 83 page

LPC2921_23_25_1

Preliminary data sheet

Rev. 01 — 15 June 2009

15 of 83

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

found in the speciﬁc subsystem description. Some branch clocks have special protection

since they clock vital system parts of the device and should not be switched off. See

Section 6.15.5 for more details of how to control the individual branch clocks.

Table 7.

Base clock and branch clock overview

Base clock

Branch clock name

Parts of the device clocked

by this branch clock

Remark

BASE_SAFE_CLK

CLK_SAFE

watchdog timer

[1]

BASE_SYS_CLK

CLK_SYS_CPU

ARM968E-S and TCMs

CLK_SYS_SYS

AHB bus infrastructure

CLK_SYS_PCRSS

AHB side of bridge in PCRSS

CLK_SYS_FMC

Flash-Memory Controller

CLK_SYS_RAM0

Embedded SRAM Controller 0

(16 kB)

CLK_SYS_RAM1

Embedded SRAM Controller 1

(16 kB) (LPC2925 only)

CLK_SYS_GESS

General Subsystem

CLK_SYS_VIC

Vectored Interrupt Controller

CLK_SYS_PESS

Peripheral Subsystem

[2] [4]

CLK_SYS_GPIO0

GPIO bank 0

CLK_SYS_GPIO1

GPIO bank 1

CLK_SYS_GPIO5

GPIO bank 5

CLK_SYS_IVNSS_A

AHB side of bridge of IVNSS

CLK_SYS_MSCSS_A

AHB side of bridge of MSCSS

CLK_SYS_DMA

GPDMA

CLK_SYS_USB

USB registers

BASE_PCR_CLK

CLK_PCR_SLOW

PCRSS, CGU, RGU and PMU

logic clock

[1] [3]

BASE_IVNSS_CLK

CLK_IVNSS_APB

APB side of the IVNSS

CLK_IVNSS_CANCA

CAN controller Acceptance

Filter

CLK_IVNSS_CANC0

CAN channel 0

CLK_IVNSS_CANC1

CAN channel 1

CLK_IVNSS_I2C0

I2C0

CLK_IVNSS_I2C1

I2C1

CLK_IVNSS_LIN0

LIN channel 0

CLK_IVNSS_LIN1

LIN channel 1

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