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LPC2921 датащи(PDF) 42 Page - NXP Semiconductors |
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LPC2921 датащи(HTML) 42 Page - NXP Semiconductors |
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42 / 83 page ![]() LPC2921_23_25_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 15 June 2009 42 of 83 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB 6.15.2 Clock Generation Unit (CGU0) The key features are: • Generation of 11 base clocks selectable from several embedded clock sources. • Crystal oscillator with power-down. • Control PLL with power-down. • Very low-power ring oscillator, always on to provide a safe clock. • Seven fractional clock dividers with L/D division. • Individual source selector for each base clock, with glitch-free switching. • Autonomous clock-activity detection on every clock source. • Protection against switching to invalid or inactive clock sources. • Embedded frequency counter. • Register write-protection mechanism to prevent unintentional alteration of clocks. Remark: Any clock-frequency adjustment has a direct impact on the timing of all on-board peripherals. 6.15.2.1 Functional description The clock generation unit provides 11 internal clock sources as described in Table 24. [1] Maximum frequency that guarantees stable operation of the LPC2921/2923/2925. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. Table 24. CGU0 base clocks Numbe r Name Frequency (MHz) [1] Description 0 BASE_SAFE_CLK 0.4 base safe clock (always on) 1 BASE_SYS_CLK 125 base system clock 2 BASE_PCR_CLK 0.4 [2] base PCR subsystem clock 3 BASE_IVNSS_CLK 125 base IVNSS subsystem clock 4 BASE_MSCSS_CLK 125 base MSCSS subsystem clock 5 BASE_ICLK0_CLK 125 base internal clock 0, for CGU1 6 BASE_UART_CLK 125 base UART clock 7 BASE_SPI_CLK 50 base SPI clock 8 BASE_TMR_CLK 125 base timers clock 9 BASE_ADC_CLK 4.5 base ADCs clock 10 reserved - - 11 BASE_ICLK1_CLK 125 base internal clock 1, for CGU1 |
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