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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC2921 датащи(PDF) 43 Page - NXP Semiconductors |
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LPC2921 датащи(HTML) 43 Page - NXP Semiconductors |
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43 / 83 page  LPC2921_23_25_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 15 June 2009 43 of 83 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See Figure 9. LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer). To prevent the device from losing its clock source LP_OSC cannot be put into power-down. The crystal oscillator can be used as source for high-frequency clocks or as an external clock input if a crystal is not connected. Secondary clock generators are a PLL and seven fractional dividers (FDIV0:6). The PLL has three clock outputs: normal, 120 ° phase-shifted and 240° phase-shifted. Fig 9. Block diagram of the CGU0 (see Table 24 for all base clocks) 400 kHz LP_OSC PLL FDIV0 EXTERNAL OSCILLATOR FDIV1 FDIV6 OUT 0 OUT 1 OUT 11 002aae147 clkout clkout120 clkout240 CLOCK GENERATION UNIT (CGU0) FREQUENCY MONITOR CLOCK DETECTION AHB TO DTL BRIDGE BASE_SYS_CLK BASE_ICLK1_CLK OUT 3 BASE_IVNSS_CLK OUT 2 BASE_PCR_CLK BASE_SAFE_CLK |
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