LPC2921 datasheet(17/83 Pages) NXP

17 / 83 page

LPC2921_23_25_1

Preliminary data sheet

Rev. 01 — 15 June 2009

17 of 83

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

6.8 Flash memory controller

The ﬂash memory has a 128-bit wide data interface and the ﬂash controller offers two

128-bit buffer lines to improve system performance. The ﬂash has to be programmed

initially via JTAG. In-system programming must be supported by the bootloader. Flash

memory contents can be protected by disabling JTAG access. Suspension of burning or

erasing is not supported.

The Flash Memory Controller (FMC) interfaces to the embedded ﬂash memory for two

tasks:

• Memory data transfer

• Memory conﬁguration via triggering, programming, and erasing

The key features are:

• Programming by CPU via AHB

• Programming by external programmer via JTAG

• JTAG access protection

• Burn-ﬁnished and erase-ﬁnished interrupt

6.8.1 Functional description

After reset ﬂash initialization is started. During this initialization, ﬂash access is not

possible and AHB transfers to ﬂash are stalled, blocking the AHB bus.

During ﬂash initialization, the index sector is read to identify the status of the JTAG access

protection and sector security. If JTAG access protection is active, the ﬂash is not

accessible via JTAG. In this case, ARM debug facilities are disabled and ﬂash-memory

contents cannot be read. If sector security is active, only the unsecured sections can be

read.

Flash can be read synchronously or asynchronously to the system clock. In synchronous

operation, the ﬂash goes into standby after returning the read data. Started reads cannot

be stopped, and speculative reading and dual buffering are therefore not supported.

With asynchronous reading, transfer of the address to the ﬂash and of read data from the

ﬂash is done asynchronously, giving the fastest possible response time. Started reads can

be stopped, so speculative reading and dual buffering are supported.

Buffering is offered because the ﬂash has a 128-bit wide data interface while the AHB

interface has only 32 bits. With buffering a buffer line holds the complete 128-bit ﬂash

word, from which four words can be read. Without buffering every AHB data port read

starts a ﬂash read. A ﬂash read is a slow process compared to the minimum AHB cycle

time, so with buffering the average read time is reduced improving system performance.

With single buffering, the most recently read ﬂash word remains available until the next

ﬂash read. When an AHB data-port read transfer requires data from the same ﬂash word

as the previous read transfer, no new ﬂash read is done and the read data is given without

wait cycles.

When an AHB data port read transfer requires data from a different ﬂash word to that

involved in the previous read transfer, a new ﬂash read is done and wait states are given

until the new read data is available.

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