LPC2921 datasheet(14/83 Pages) NXP

14 / 83 page

LPC2921_23_25_1

Preliminary data sheet

Rev. 01 — 15 June 2009

14 of 83

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

Two of the base clocks generated by the CGU0 are used as input into a second, dedicated

CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate the base

clock for the USB controller and one base clock for an independent clock output.

6.7.2 Base clock and branch clock relationship

Table 7 contains an overview of all the base blocks in the LPC2921/2923/2925 and their

derived branch clocks. A short description is given of the hardware parts that are clocked

with the individual branch clocks. In relevant cases more detailed information can be

Fig 4.

LPC2921/2923/2925 overview of clock areas

TIMER0/1 MTMR

PWM0/1/2/3

ADC1/2

QEI

modulation and sampling

control subsystem

BASE_MSCSS_CLK

branch

clocks

branch

clocks

BASE_ADC_CLK

BASE_ICLK0_CLK

BASE_ICLK1_CLK

CAN0/1

GLOBAL

ACCEPTANCE

FILTER

LIN0/1

I2C0/1

networking subsystem

BASE_IVNSS_CLK

branch

clocks

RESET/CLOCK

GENERATION

POWER

MANAGEMENT

power control subsystem

BASE_PCR_CLK

branch

clock

GPIO0/1/5

TIMER0/1/2/3

SPI0/1/2

UART0/1

WDT

BASE_SYS_CLK

CPU

AHB MULTILAYER MATRIX

VIC

GPDMA

USB REGISTERS

FLASH/SRAM

general subsytem

peripheral subsystem

AHB TO APB BRIDGES

SYSTEM CONTROL

EVENT ROUTER

CFID

branch

clocks

BASE_SAFE_CLK

BASE_UART_CLK

BASE_SPI_CLK

BASE_TMR_CLK

002aae238

CGU0

CGU1

BASE_USB_CLK

BASE_OUT_CLK

USB

CLOCK

OUT

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