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LPC2921 датащи(PDF) 41 Page - NXP Semiconductors

номер детали LPC2921
подробное описание детали  ARM9 microcontroller with CAN, LIN, and USB
PDF  83 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2921 датащи(HTML) 41 Page - NXP Semiconductors

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LPC2921_23_25_1
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 — 15 June 2009
41 of 83
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
6.15.1 Clock description
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
PMU internal logic, see Section 6.7.2. CLK_SYS_PCRSS is derived from
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
Fig 8.
Power, Clock, and Reset control SubSystem (PCRSS) block diagram
002aae249
AHB2DTL
BRIDGE
RESET OUTPUT
DELAY LOGIC
INPUT
DEGLITCH/
SYNC
branch
clocks
grant
request
wakeup_a
AHB_RST
SCU_RST
WARM_RST
COLD_RST
PCR_RST
RGU_RST
POR_RST
RST (device pin)
reset from watchdog counter
EXTERNAL
OSCILLATOR
PMU
REGISTERS
CLOCK
ENABLE
CONTROL
CLOCK
GATES
LOW POWER
RING
OSCILLATOR
CGU0
REGISTERS
RGU
REGISTERS
POR
OUT0
OUT1
OUT5
OUT7
OUT9
OUT6
OUT11
OUT0
OUT2
PLL
FDIV[6:0]
PLL
FDIV
CGU0
CGU1
PMU
RGU
AHB
master
disable:



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