LPC2921 datasheet(9/83 Pages) NXP

9 / 83 page

LPC2921_23_25_1

Preliminary data sheet

Rev. 01 — 15 June 2009

9 of 83

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

[1]

Bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5 V tolerant; TTL with hysteresis; programmable pull-up /

pull-down / repeater.

[2]

USB pad.

[3]

Analog pad; analog I/O.

[4]

Analog I/O pad.

Functional description

6.1 Architectural overview

The LPC2921/2923/2925 consists of:

• An ARM968E-S processor with real-time emulation support

• An AMBA multilayer Advanced High-performance Bus (AHB) for interfacing to the

on-chip memory controllers

• Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller

and the Power, Clock and Reset Control SubSystem (PCRSS).

• Three ARM Peripheral Buses (APB - a compatible super set of ARM's AMBA

advanced peripheral bus) for connection to on-chip peripherals clustered in

subsystems.

• One ARM Peripheral Bus for event router and system control.

The LPC2921/2923/2925 conﬁgures the ARM968E-S processor in little-endian byte order.

All peripherals run at their own clock frequency to optimize the total system power

consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer

one transaction deep. This implies that when the ARM968E-S issues a buffered write

action to a register located on the APB side of the bridge, it continues even though the

actual write may not yet have taken place. Completion of a second write to the same

subsystem will not be executed until the ﬁrst write is ﬁnished.

6.2 ARM968E-S processor

The ARM968E-S is a general purpose 32-bit RISC processor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers (CISC). This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective controller

core.

Amongst the most compelling features of the ARM968E-S are:

• Separate directly connected instruction and data Tightly Coupled Memory (TCM)

interfaces.

P0[23]/IN2[7]/

PMAT2[5]/A19

99[4]

GPIO 0, pin 23

ADC2 IN7

PWM2 MAT5

TDI

100[1]

IEEE 1149.1 data in, pulled up internally

Table 3.

LQFP100 pin assignment …continued

Pin name

Description

Function 0 (default)

Function 1

Function 2

Function 3

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